IEPE Sensor
In IEPE mode the negative input of each channel is internally grounded. Best measurement results can be obtained if the negative input pin of
each channel is used for the coaxial ground/shield. The return current then flows straight to the channel ground and not to the common card
ground.
Input ranges
±
10 mV,
±
20 mV,
±
50 mV,
±
0.1 V,
±
0.2 V,
±
0.5 V,
±
1 V,
±
2 V,
±
5 V,
±
10 V,
±
20 V
Over voltage protection
-
1 V to 22 V DC
IEPE gain error
0.1% of Full Scale
±
300 μV
IEPE gain error drift
±
10 ppm/°C (
±
6 ppm/°F)
IEPE compliance voltage
≥ 22 V
Excitation current
2, 4, 6, 8 mA, software selectable
Excitation current accuracy
±
5%
Coupling time constant
1.5 s
Lower bandwidth
-
3 dB @ 0.11 Hz
Maximum cable length
100 m (RG
-
58)
Wire diagnostics
Open and shorted IEPE wiring detected (Requires Perception V7.00 or higher)
TEDS support
Class 1, including software selectable auto detect the presence of an attached sensor
Charge Amplifier
In charge mode the negative input of each channel is internally grounded. Best measurement results can be obtained if the negative input pin
of each channel is used for the coaxial ground/shield. The return current then flows straight to the channel ground and not to the common card
ground.
Input ranges
±
10 pC,
±
20 pC,
±
50 pC,
±
100 pC,
±
200 pC,
±
0.5 nC,
±
1 nC,
±
2 nC
Over voltage protection
±
20 V DC
Charge gain error
±
2% of Full Scale
Charge gain error drift
±
30 ppm/°C (
±
17 ppm/°F)
-
3 dB high pass bandwidth limit
1 Hz
-
3 dB low pass bandwidth limit
33 kHz
±
10% when a 650 pF source capacity is used
106 kHz
±
10% when a 250 pF source capacity is used
TEDS support
No
Analog to Digital Conversion
Sample rate; per channel
1 S/s to 250 kS/s
ADC resolution; one ADC per channel
24 bit
ADC type
Sigma Delta (Σ
-
Δ) ADC; Analog Devices AD7764BRUZ
Time base accuracy
Defined by mainframe:
±
3.5 ppm
(1)
; aging after 10 years
±
10 ppm
Binary sample rate
Supported; produces rounded BIN values when calculating FFT's
Maximum binary sample rate
256 kS/s
External time base frequency
0 S/s to 25 kS/s
External time base frequency divider
Divide external clock by 1 to 2
20
External time base level
TTL
External time base minimum pulse width
200 ns
(1)
Mainframes using Interface/Controller modules shipped before 2012:
±
30 ppm.
GEN3i
I3763-3.1 en HBM: public
1101
