Block Diagram
+
-
F
F
n
-1
n
-1
z
-1
z
-1
Σ
a
1
a
2
b
2
b
1
x
(n)
y
(n)
A
A
T
Channel 1 to 4
Probe Power
+ 8 V
Amplifier
Analog Anti-Alias Filter
ADC
Digital Filter &
Sample Rate selection
Sample Rate
Channel &
Card Trigger
Communication
& Memory &
Recording control
Synchronization
& Sample Rate
100 MHz
100 MHz
Backplane
System Trigger Bus
Communication and
Data Streaming
Acquisition Control
Master Time Base
1010
AC/DC/GND
Figure A.51:
Block Diagram
Note The specifications listed are valid for cards that have been calibrated and are used in the same mainframe and
slots as they were at the time of calibration. When the card is removed from its original location and placed in
another slot and/or mainframe, the Offset error, Gain error and MSE specifications are expected to increase
(up to double the original specification) due to thermal differences within the configurations. All specifications
are defined at 23 °C
±
2 °C, unless specified differently.
GEN3i
438
I3763-3.1 en HBM: public
