12.10.5
GN6470 and GN4070 Counter mode pinning
When in counter mode, Event Bits 53 through 63 are used to provide the counter
functionality. These bits are located on the bottom connector as follows:
11 - 54: dir 1
10 - 55: res 1
12 - 53: inp 1
8 - 57: inp 2
6 - 59: res 2
7 - 58: dir 2
4 - 61: inp 3
3 - 62: dir 3
xx = pin number
yy = event number
aaa = function
N = channel number
xx - yy: aaa N
2 - 63: res 3
Figure 12.69:
Counter pinning layout
Table 12.8: Counter bit connector pinning
PIN #
EVENT
COUNTER FUNCTION
12
Event Bit 53
1
Counter input
11
Event Bit 54
1
Direction: increment / decrement
10
Event Bit 55
1
Reset
8
Event Bit 57
2
Counter input
7
Event Bit 58
2
Direction: increment / decrement
6
Event Bit 59
2
Reset
4
Event Bit 61
3
Counter input
3
Event Bit 62
3
Direction: increment / decrement
2
Event Bit 63
3
Reset
In the Perception software, the event bits are combined within one channel and
labeled as CH1_1 through CH1_64. The counter/timer channels are referred to
as CH2 through CH4.
Counter input
The counter input is the actual signal input. The counter value
is modified on each rising edge of this signal. The maximum input rate is 10
Mhz.
GEN3i
298
I3763-3.1 en HBM: public
