
9-2
ALPS Advanced Line Protection System
GE Power Management
9.1 SPARES
9 SERVICING
9
Table 9–1: COMPONENTS TESTED DURING START-UP TESTS
COMPONENT
METHOD
PROCESSO
R
NATURE
Flash Memory (PROM)
CRC-type check
960 CPU
Critical
EPROM
Checksum on DSP board
DSP
Critical
Local RAM
Patterns to check for stuck bits, stuck address lines, cross-
talk between adjacent bits
960 CPU
DSP
Critical
Shared RAM
Same as Local RAM
Both
Critical
Nonvolatile RAM
CAPRAM
Serial RAM
CRC-type check on settings area; checksum on fault
storage area:
duplicate locations on serial NVRAM
960 CPU
Critical if settings area or
serial NVRAM
Timer Chip
Test all processor timers and their interrupts
960 CPU
Critical if ANI logic; non-
critical if 960
Interrupt Controller
Test all 960 internal interrupts
960 CPU
Critical
Serial Chips
Wraparound and interrupt tests for serial interface
960 CPU
Non-critical
A/D Controller
DMA Interface
960 CPU
Critical
Digital Output Circuitry
Loop-back test
960 CPU
Critical
Digital Input Circuitry
Comparison of bits read via two separate optocouplers
960 CPU
Non-critical, turn off pilot
protection
Real-Time Clock
Test of real-time clock operation and interrupts
960 CPU
Non-critical
Table 9–2: RUN-TIME BACKGROUND SELF-TESTS
COMPONENT
METHOD
PROCESSOR
NATURE
Flash Memory (PROM)
CRC-type check
960 CPU
Critical, restart
EPROM
Checksum type check
DSP
Critical, restart
RAM
Protection values checked for correctness;
Configurable logic checked for validity
960 CPU
Critical, restart
Nonvolatile RAM
CRC-type check on settings area
960 CPU
Non-critical
CAPRAM
Checksum on fault storage area
960 CPU
Table 9–3: RUN-TIME FOREGROUND SELF-TESTS
COMPONENT
METHOD
PROCESSOR
NATURE
A/D Controller
DMA interface
960 CPU
Critical
Digital Input Circuitry
Comparison of bits read via two separate
optocouplers
960 CPU
Non-critical, turn off pilot
protection
Digital Output Circuitry
Loop-back test
960 CPU
Critical, restart
Trip Circuit Continuity
Bit read via bus
960 CPU
Non-critical
LUI
Operator initiated, visual feedback
960 CPU
Non-critical