3
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Contents
1.16.5
SYSJMBO0 Register
............................................................................................
1.16.6
SYSJMBO1 Register
............................................................................................
1.16.7
SYSUNIV Register
...............................................................................................
1.16.8
SYSSNIV Register
...............................................................................................
1.16.9
SYSRSTIV Register
.............................................................................................
2
Power Management Module (PMM) and Supply Voltage Supervisor (SVS)
.................................
2.1
Power Management Module (PMM) Introduction
......................................................................
2.2
PMM Operation
.............................................................................................................
2.2.1
V
CORE
and the Regulator
..........................................................................................
2.2.2
Supply Voltage Supervisor
.......................................................................................
2.2.3
Supply Voltage Supervisor - Power-Up
........................................................................
2.2.4
LPM3.5 and LPM4.5
..............................................................................................
2.2.5
Brownout Reset (BOR)
...........................................................................................
2.2.6
RST/NMI
............................................................................................................
2.2.7
PMM Interrupts
....................................................................................................
2.2.8
Port I/O Control
....................................................................................................
2.3
PMM Registers
.............................................................................................................
2.3.1
PMMCTL0 Register (offset = 00h) [reset = 9640h]
...........................................................
2.3.2
PMMCTL1 Register (offset = 02h) [reset = 9600h]
...........................................................
2.3.3
PMMIFG Register (offset = 0Ah) [reset = 0000h]
.............................................................
2.3.4
PM5CTL0 Register (offset = 10h) [reset = 0001h]
............................................................
3
Clock System (CS) Module
..................................................................................................
3.1
Clock System Introduction
................................................................................................
3.2
Clock System Operation
...................................................................................................
3.2.1
CS Module Features for Low-Power Applications
............................................................
3.2.2
LFXT Oscillator
....................................................................................................
3.2.3
HFXT Oscillator
....................................................................................................
3.2.4
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
..................................................
3.2.5
Module Oscillator (MODOSC)
...................................................................................
3.2.6
Digitally Controlled Oscillator (DCO)
............................................................................
3.2.7
Operation From Low-Power Modes, Requested by Peripheral Modules
..................................
3.2.8
CS Module Fail-Safe Operation
................................................................................
3.2.9
Synchronization of Clock Signals
..............................................................................
3.3
MemoryMap Registers
...................................................................................................
3.3.1
CTL0 Register (Offset = 0h) [reset = 9600h]
.................................................................
3.3.2
CTL1 Register (Offset = 2h) [reset = Ch]
.....................................................................
3.3.3
CTL2 Register (Offset = 4h) [reset = 33h]
....................................................................
3.3.4
CTL3 Register (Offset = 6h) [reset = 33h]
....................................................................
3.3.5
CTL4 Register (Offset = 8h) [reset = CDC9h]
...............................................................
3.3.6
CTL5 Register (Offset = Ah) [reset = 00C5h]
................................................................
3.3.7
CTL6 Register (Offset = Ch) [reset = 7h]
.....................................................................
4
CPUX
..............................................................................................................................
4.1
MSP430X CPU (CPUX) Introduction
...................................................................................
4.2
Interrupts
...................................................................................................................
4.3
CPU Registers
............................................................................................................
4.3.1
Program Counter (PC)
..........................................................................................
4.3.2
Stack Pointer (SP)
...............................................................................................
4.3.3
Status Register (SR)
............................................................................................
4.3.4
Constant Generator Registers (CG1 and CG2)
.............................................................
4.3.5
General-Purpose Registers (R4 to R15)
......................................................................
4.4
Addressing Modes
........................................................................................................
4.4.1
Register Mode
....................................................................................................
4.4.2
Indexed Mode
....................................................................................................