ESITESTD
ESITESTS1(tsm)
+
1
0
ESICH0
ESICH1
ESICH2
00
01
10
11
ESICH3
1
0
ESICI
ESICISEL
ESICA1X
ESICACI3
10
11
01
00
ESITCH0x
2
ESITCH1x
2
ESICHx(tsm)
2
Sync.
00
01
10
11
00
01
10
11
S/H
S/H
S/H
ESISHTSM
ESICOM
Sample/Hold
2
DAC 12 Bit
ESIDAC1R0
ESIDAC1R1
ESIDAC1R2
ESIDAC1R3
ESIDAC1R4
ESIDAC1R5
ESIDAC1R6
ESIDAC1R7
ESISH
ESICA(tsm)
ESIDAC(tsm)
ESICI0
ESICI1
ESICI2
ESICI3
S/H
VMID
ESIVMIDEN
00
01
10
11
Excite
Excite
Excite
Excite
ESITEN
Excitation
ESILCEN(tsm)
ESIEX(tsm)
TESTDX
-
DAC1
ESITEST1
ESITEST0
ESIC1OUT
ESICA1INV
Channel Select
Logic
ESIC1OUT
Selected input channel is 00b.
Selected input channel is 01b
Selected input channel is 10b
Selected input channel is 11b or test cycle is in progress.
Hysteresis programmable with the two registers.
Hysteresis programmable with the two registers.
Hysteresis programmable with the two registers.
Hysteresis programmable with the two registers.
AV
CC
8 MSB
4 LSB
+
en
en
ESI Operation
968
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Extended Scan Interface (ESI)
Figure 37-2. ESI Analog Front End AFE1 Block Diagram
The AFE2 is disabled after reset. AFE2 can be enabled by setting the ESICA2EN and ESIDAC2EN bits. If
the AFE2 is disabled (ESICA2EN = 0 and ESIDAC2EN = 0), the AFE2 comparator output is always low (0
level).