HSPLL Registers
484
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
High-Speed PLL (HSPLL)
20.6.1 HSPLLIIDX Register (Offset = 0h) [reset = 0h]
HSPLLIIDX is shown in
and described in
.
Return to
Interrupt Index Register.
Note: This register is word accessible. A byte access is also allowed but not recommended. Either high
byte or low byte access alone can clear the pending interrupt flag.
Figure 20-3. HSPLLIIDX Register
15
14
13
12
11
10
9
8
IIDX
R-
7
6
5
4
3
2
1
0
IIDX
RESERVED
R-
R-
Table 20-2. HSPLLIIDX Register Field Descriptions
Bit
Field
Type
Reset
Description
15-1
IIDX
R
HSPLL Interrupt Vector Value. Read only. It generates a value that
can be used as address offset for fast interrupt service routine
handling. On each read, only one interrupt is indicated. On a read,
the current interrupt (highest priority) is automatically cleared by the
hardware and the corresponding interrupt flag in RIS and MISC are
cleared as well. After a read from the CPU (not from the debug
interface), the register must be updated with the next highest priority
interrupt, if none are pending, then it should display 0h.
If the interrupt displayed by the IIDX register (highest priority pending
interrupt) is cleared in the MISC through a software write of 1 in the
corresponding bit field, the IIDX register shall be updated and the
next priority interrupt (if any) be displayed.
Reset type: PUC
0h (R) = No Interrupt pending
1h (R) = Interrupt Source: PLLUNLOCK; Interrupt Priority: Highest
2h (R) = Reserved; Interrupt Priority: Lowest
0
RESERVED
R
0h
Reserved