ADC12_B Registers
899
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
ADC12_B
34.3.5 ADC12MEMx Register (x = 0 to 31)
ADC12_B Conversion Memory x Register (x = 0 to 31)
Figure 34-18. ADC12MEMx Register
15
14
13
12
11
10
9
8
Conversion Results
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
Conversion Results
rw
rw
rw
rw
rw
rw
rw
rw
Table 34-8. ADC12MEMx Register Description
Bit
Field
Type
Reset
Description
15-0
Conversion Results
RW
undefined
If ADC12DF = 0: The 12-bit conversion results are right justified. Bit 11 is the
MSB. Bits 15-12 are 0 in 12-bit mode, bits 15-10 are 0 in 10-bit mode, and bits
15-8 are 0 in 8-bit mode. If the user writes to the conversion memory registers,
the results are corrupted.
If ADC12DF = 1: The 12-bit conversion results are left-justified 2s-complement
format. Bit 15 is the MSB. Bits 3-0 are 0 in 12-bit mode, bits 5-0 are 0 in 10-bit
mode, and bits 7-0 are 0 in 8-bit mode. The data is stored in the right-justified
format and is converted to the left-justified 2s-complement format during read
back. If the user writes to the conversion memory registers, the results are
corrupted.