Operating Modes
58
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
System Resets, Interrupts, and Operating Modes, System Control Module
(SYS)
(1)
This bit is automatically reset when exiting low-power modes. See
for details.
(2)
The low-power modes and, hence, the system clocks can be affected by the clock request system. See the
chapter for
details.
Table 1-2. Operation Modes
SCG1
(1)
SCG0
OSCOFF
(1)
CPUOFF
(1)
Mode
CPU and Clocks Status
(2)
0
0
0
0
Active
CPU, MCLK are active.
ACLK is active. SMCLK optionally active (SMCLKOFF = 0).
DCO is enabled if sources ACLK, MCLK, or SMCLK (SMCLKOFF = 0).
DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF =
0).
0
0
0
1
LPM0
CPU, MCLK are disabled.
ACLK is active. SMCLK optionally active (SMCLKOFF = 0).
DCO is enabled if sources ACLK or SMCLK (SMCLKOFF = 0).
DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF =
0).
0
1
0
1
LPM1
CPU, MCLK are disabled.
ACLK is active. SMCLK optionally active (SMCLKOFF = 0).
DCO is enabled if sources ACLK or SMCLK (SMCLKOFF = 0).
DCO bias is enabled if DCO is enabled or DCO sources MCLK or SMCLK (SMCLKOFF =
0).
1
0
0
1
LPM2
CPU, MCLK are disabled.
ACLK is active. SMCLK is disabled.
1
1
0
1
LPM3
CPU, MCLK are disabled.
ACLK is active. SMCLK is disabled.
1
1
1
1
LPM4
CPU and all clocks are disabled.
1
1
1
1
LPM3.5
When PMMREGOFF = 1, regulator is disabled. No memory retention. In this mode, RTC
operation is possible when configured properly. See the
RTC
module for further details.
1
1
1
1
LPM4.5
When PMMREGOFF = 1, regulator is disabled. No memory retention. In this mode, all
clock sources are disabled; that is, no RTC operation is possible.
1.4.1 Low-Power Modes and Clock Requests
A peripheral module requests its clock sources automatically from the clock system (CS) module if it is
required for its proper operation, regardless of the current power mode of operation. Refer to the
"Operation From Low-Power Modes, Requested by Peripheral Modules" section in the
chapter.
Because of the clock request mechanism the system might not reach the low-power modes requested by
the bits set in the CPU's status register SR as listed in
Table 1-3. Requested vs Actual LPM
Requested LPM
(SR Bits according to
Actual LPM...
If No Clock Requested
If Only ACLK Requested
If SMCLK Requested
LPM0
LPM0
LPM0
LPM0
LPM1
LPM1
LPM1
LPM1
LPM2
LPM2
LPM2
LPM0
LPM3
LPM3
LPM3
LPM1
LPM4
LPM4
LPM3
LPM1