System Control Module (SYS) Introduction
48
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
System Resets, Interrupts, and Operating Modes, System Control Module
(SYS)
1.1
System Control Module (SYS) Introduction
SYS is responsible for the interaction between various modules throughout the system. The functions that
SYS provides for are not inherent to the modules themselves. Address decoding, bus arbitration, interrupt
event consolidation, and reset generation are some examples of the many functions that SYS provides.
1.2
System Reset and Initialization
The system reset circuitry is shown in
and sources a brownout reset (BOR), a power-on reset
(POR), and a power-up clear (PUC). Different events trigger these reset signals and different initial
conditions exist depending on which signal was generated.
A BOR is a device reset. A BOR is generated only by the following events:
•
Powering up the device
•
Low signal on the RST/NMI pin when configured in the reset mode
•
Wake-up event from LPMx.5 (that is, LPM3.5 or LPM4.5) mode
•
SVS
H
low condition, when enabled (see the
chapter for details)
•
Software BOR event (see the
chapter for details)
A POR is always generated when a BOR is generated, but a BOR is not generated by a POR. The
following events trigger a POR:
•
BOR signal
•
Software POR event (see the
chapter for details)
A PUC is always generated when a POR is generated, but a POR is not generated by a PUC. The
following events trigger a PUC:
•
POR signal
•
Watchdog timer expiration when watchdog mode only (see the
chapter for details)
•
Watchdog timer password violation (see the
chapter for details)
•
FRAM memory password violation (see the
chapter for details)
•
Power Management Module password violation (see the
chapter for details)
•
Memory Protection Unit password violation (see the
chapter for details)
•
Memory segment violation (see the
chapter for details)
•
Clock System password violation (see the
chapter for details)
•
Fetch from peripheral area
•
Uncorrectable FRAM bit error detection
NOTE:
The number and type of resets available may vary from device to device. See the device-
specific data sheet for all reset sources available.