SDHS Registers
609
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Sigma-Delta High Speed (SDHS)
22.5.12 SDHSCTL3 Register (Offset = 16h) [reset = 0h]
SDHSCTL3 is shown in
and described in
Return to
SDHS Control Register 3
Figure 22-38. SDHSCTL3 Register
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
TRIGEN
R-0h
R/W-0h
Table 22-23. SDHSCTL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
15-1
RESERVED
R
0h
Reserved. Always reads as 0.
0
TRIGEN
R/W
0h
SDHS Trigger Enable bit. This bit enables SDHS Trigger Source and
lock SDHS registers.
Note:
This bit is used to inform SDHS that register configuration has been
completed. This bit must be written as 1 before applying
SDHS_PWR_UP signal.
Once this bit is asserted, SDHSCTL0, SDHSCTL1, SDHSCTL2,
SDHSCTL7, SDHSWINHITH, SDHSWINLOTH, and SDHSDTCDA
registers are locked (not allowed to be modified). This bit is locked
once a SDHS_PWR_UP signal is applied. See
SDHSCTL5.SDHS_LOCK for the sequence of SDHS register
configuration.
Reset type: PUC
0h (R/W) = SDHS Trigger is disabled. Once this bit is de-asserted,
SDHSCTL0, SDHSCTL1, SDHSCTL2, SDHSCTL7, SDHSWINHITH,
SDHSWINLOTH, and SDHSDTCDA registers are unlocked (allowed
to be modified).
1h (R/W) = SDHS Trigger is enabled. Once this bit is asserted,
SDHSCTL0, SDHSCTL1, SDHSCTL2, SDHSCTL7,SDHSWINHITH,
SDHSWINLOTH, and SDHSDTCDA registers are locked (not
allowed to be modified).