ESI Operation
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SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Extended Scan Interface (ESI)
37.2.2.1 TSM Operation
Starting of a TSM sequence depends on the selected trigger. Possible triggers are the control bit
ESISTART, the divided ACLK and an or combination of these two triggers (ESISTART or divided ACLK).
If the divided ACLK is chosen, the TSM automatically starts and re-starts periodically based on a divided
ACLK start signal selected with the ESIDIV2x bits, the ESIDIV3Ax and ESIDIV3Bx bits when ESITSMRP
= 0. For example, if ESIDIV2x, ESIDIV3Ax, and ESIDIV3Bx are configured to 270 ACLK cycles, then the
TSM automatically starts every 270 ACLK cycles. When ESITSMRP = 1 the TSM restarts immediately
with the ESITSM0 state at the end of the previous sequence i.e. with the next ACLK cycle after
encountering a state with ESISTOP = 1. The ESIIFG2 interrupt flag is set when the TSM starts.
The ESIDIV2x, ESIDIV3Ax, and ESIDIV3Bx bits may be updated anytime during operation. When
updated, the current TSM sequence will continue with the old settings until the last state of the sequence
completes. The new settings will take affect at the start of the next sequence.
Setting ESISTART bit is another trigger for starting a TSM sequence. The ESISTART bit is set as long as
the actual TSM sequence is in progress. As soon as the TSM sequence is completed and ESITSM0
register is again active for idle state configuration the ESISTART bit is automatically cleared. In case
ESISTART is the only source for a start trigger (ESITSMTRG = 01) an ACLK synchronization sequence is
performed, which may take up to 2.5 ACLK cycles. For all other cases no special synchronization is
needed and TSM starts with the appropriate positive ACLK edge.
NOTE:
It is important to set the ESISTOP(tsm) bit at least once the control registers ESITSM2 to
ESITSM31. The ESISTOP(tsm) control bit ensures that a user-defined TSM sequence is
terminated and the TSM progressing is switching into idle mode awaiting the next start
trigger.
37.2.2.2 TSM Idle Condition Selectable With ESITSM0
ESITSM0 register is used for two different tasks. First, by definition ESITSM0 register is always the first
ESITSMx register within a TSM sequence. The second purpose of ESITSM0 is to define the settings of
the analog front ends during idle time; idle time means no TSM sequence is in progress.
When ESITSM0 defines the AFE1 and AFE2 settings in idle time only some of the ESITSMx control bits
are functional. These functional bits are ESICLKON, ESIRSON, ESIEX, ESILCEN, and ESICHx. Some
bits do not have any effect in idle mode, like ESIDAC, ESICA, ESIREPEATx bits and ESICLK bit; the
ESIREPEATx bits and ESICLK bit are only utilized when ESITSM0 is used within a TSM sequence.
ESIDAC and ESICA bits should be '0' in ESITSM0 state for reduced current consumption.
Note that changing ESITSM0 register gets effective not before the next TSM sequence is started. This has
to be considered especially after powering up the device and doing the first initialization of the ESI.
37.2.2.3 TSM Control of the AFE
The TSM controls the AFE with the ESICHx, ESILCEN, ESIEX, ESICA, ESICLKON, ESIRSON,
ESITESTS1, ESIDAC, ESISTOP, and ESICLK bits. When any of these bits are set, their corresponding
signal(s), ESICHx(tsm), ESILCEN(tsm), ESIEX(tsm), ESICA(tsm), ESICLKON(tsm), ESIRSON(tsm),
ESITESTS1(tsm), ESIDAC(tsm), ESISTOP(tsm), and ESICLK(tsm) are high for the duration of the state.
Otherwise, the corresponding signal(s) are low.
37.2.2.4 TSM State Duration
The duration of each state is individually configurable with the ESIREPEATx bits. The duration of each
state is ESIR 1 times the selected clock source. For example, if a state were defined with
ESIREPEATx = 3 and ESICLK = 1, the duration of that state would be 4 x ACLK cycles. Because of clock
synchronization, the duration of each state is affected by the clock source for the previous state, as shown
in
.