HSPLL Registers
489
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
High-Speed PLL (HSPLL)
20.6.6 HSPLLISR Register (Offset = Ah) [reset = 0h]
HSPLLISR is shown in
and described in
Return to
Interrupt Flag Set Register. Read as zero.
Figure 20-8. HSPLLISR Register
15
14
13
12
11
10
9
8
RESERVED
R-0h
7
6
5
4
3
2
1
0
RESERVED
PLLUNLOCK
R-0h
W-0h
Table 20-7. HSPLLISR Register Field Descriptions
Bit
Field
Type
Reset
Description
15-1
RESERVED
R
0h
Reserved
0
PLLUNLOCK
W
0h
PLL Unlock Interrupt Set bit. Write 1 to set RIS.PLLUNLOCK bit
Reset type: PUC