DMA Operation
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SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
DMA Controller
11.2.3 Initiating DMA Transfers
Each DMA channel is independently configured for its trigger source with the DMAxTSEL. The
DMAxTSEL bits should be modified only when the DMAEN bit in the DMAxCTL register is 0. Otherwise,
unpredictable DMA triggers may occur.
describes the trigger operation for each type of
module. See the device-specific data sheet for the list of triggers available, along with their respective
DMAxTSEL values.
When selecting the trigger, the trigger must not have already occurred, or the transfer does not take place.
11.2.3.1 Edge-Sensitive Triggers
When DMALEVEL = 0, edge-sensitive triggers are used, and the rising edge of the trigger signal initiates
the transfer. In single-transfer mode, each transfer requires its own trigger. When using block or burst-
block modes, only one trigger is required to initiate the block or burst-block transfer.
11.2.3.2 Level-Sensitive Triggers
When DMALEVEL = 1, level-sensitive triggers are used. For proper operation, level-sensitive triggers can
only be used when external trigger DMAE0 is selected as the trigger. DMA transfers are triggered as long
as the trigger signal is high and the DMAEN bit remains set.
The trigger signal must remain high for a block or burst-block transfer to complete. If the trigger signal
goes low during a block or burst-block transfer, the DMA controller is held in its current state until the
trigger goes back high or until the DMA registers are modified by software. If the DMA registers are not
modified by software, when the trigger signal goes high again, the transfer resumes from where it was
when the trigger signal went low.
When DMALEVEL = 1, transfer modes selected when DMADT = {0, 1, 2, 3} are recommended, because
the DMAEN bit is automatically reset after the configured transfer.