AES Accelerator Registers
426
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
AES256 Accelerator
14.3.8 AESAXIN Register
AES Accelerator XORed Data In Register (No Trigger)
Figure 14-21. AESAXIN Register
15
14
13
12
11
10
9
8
AESXIN1x
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
7
6
5
4
3
2
1
0
AESXIN0x
w-0
w-0
w-0
w-0
w-0
w-0
w-0
w-0
Table 14-19. AESAXIN Register Description
Bit
Field
Type
Reset
Description
15-8
AESXIN1x
W
0h
AES data in byte n+1 when AESAXIN is written as word. Do not use these bits
for byte access. Do not mix word and byte access. Always reads as zero.
7-0
AESXIN0x
W
0h
AES data in byte n when AESAXIN is written as word. AES next data in byte
when AESAXIN_L is written as byte. Do not mix word and byte access. Always
reads as zero.