eUSCI_B I2C Registers
846
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Enhanced Universal Serial Communication Interface (eUSCI) – I
2
C Mode
Table 32-4. UCBxCTLW0 Register Description (continued)
Bit
Field
Type
Reset
Description
4
UCTR
RW
0h
Transmitter/receiver
0b = Receiver
1b = Transmitter
3
UCTXNACK
RW
0h
Transmit a NACK. UCTXNACK is automatically cleared after a NACK is
transmitted. Only for slave receiver mode.
0b = Acknowledge normally
1b = Generate NACK
2
UCTXSTP
RW
0h
Transmit STOP condition in master mode. Ignored in slave mode. In master
receiver mode, the STOP condition is preceded by a NACK. UCTXSTP is
automatically cleared after STOP is generated. This bit is a don't care, if
automatic UCASTPx is different from 01 or 10.
0b = No STOP generated
1b = Generate STOP
1
UCTXSTT
RW
0h
Transmit START condition in master mode. Ignored in slave mode. In master
receiver mode, a repeated START condition is preceded by a NACK. UCTXSTT
is automatically cleared after START condition and address information is
transmitted. Ignored in slave mode.
0b = Do not generate START condition
1b = Generate START condition
0
UCSWRST
RW
1h
Software reset enable.
0b = Disabled. eUSCI_B released for operation.
1b = Enabled. eUSCI_B logic held in reset state.