Instruction Set Description
179
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
CPUX
4.6.2.19 DINT
* DINT
Disable (general) interrupts
Syntax
DINT
Operation
0
→
GIE
or
(0FFF7h .AND. SR
→
SR / .NOT.src .AND. dst
→
dst)
Emulation
BIC #8,SR
Description
All interrupts are disabled.
The constant 08h is inverted and logically ANDed with the SR. The result is placed into
the SR.
Status Bits
Status bits are not affected.
Mode Bits
GIE is reset. OSCOFF and CPUOFF are not affected.
Example
The general interrupt enable (GIE) bit in the SR is cleared to allow a nondisrupted move
of a 32-bit counter. This ensures that the counter is not modified during the move by any
interrupt.
DINT
; All interrupt events using the GIE bit are disabled
NOP
; Required due to pipelined CPU architecture
MOV
COUNTHI,R5
; Copy counter
MOV
COUNTLO,R6
EINT
; All interrupt events using the GIE bit are enabled
NOTE:
Disable interrupt
Due to the pipelined CPU architecture, clearing the general interrupt enable (GIE) requires
special care.
•
Include at least 1 instruction between DINT and the start of an code sequence
that requires protection from interrupts. For example: Insert a NOP instruction
after the DINT.
•
Never clear the general interrupt enable (GIE) immediately after setting it. Insert
at least 1 instruction in between such sequence.
The rules above apply to all instructions that clear the general interrupt enable bit. Not
following these rules might result in unexpected CPU execution.