Timer_B Operation
667
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Timer_B
26.2 Timer_B Operation
The Timer_B module is configured with user software. The setup and operation of Timer_B is discussed in
the following sections.
26.2.1 16-Bit Timer Counter
The 16-bit timer/counter register, TBxR, increments or decrements (depending on mode of operation) with
each rising edge of the clock signal. TBxR can be read or written with software. Additionally, the timer can
generate an interrupt when it overflows.
TBxR may be cleared by setting the TBCLR bit. Setting TBCLR also clears the clock divider counter logic
(the divider setting remains unchanged) and count direction for up/down mode.
NOTE:
Modifying Timer_B registers
TI recommends stopping the timer before modifying its operation (with exception of the
interrupt enable, interrupt flag, and TBCLR) to avoid errant operating conditions.
When the timer clock is asynchronous to the CPU clock, any read from TBxR should occur
while the timer is not operating or the results may be unpredictable. Alternatively, the timer
may be read multiple times while operating, and a majority vote taken in software to
determine the correct reading. Any write to TBxR takes effect immediately.
26.2.1.1 TBxR Length
Timer_B is configurable to operate as an 8-, 10-, 12-, or 16-bit timer with the CNTL bits. The maximum
count value, TBxR
(max)
, for the selectable lengths is 0FFh, 03FFh, 0FFFh, and 0FFFFh, respectively. Data
written to the TBxR register in 8-, 10-, and 12-bit mode is right justified with leading zeros.
26.2.1.2 Clock Source Select and Divider
The timer clock can be sourced from ACLK, SMCLK, or externally from TBxCLK or INCLK. The clock
source is selected with the TBSSEL bits. The selected clock source may be passed directly to the timer or
divided by 2,4, or 8, using the ID bits. The selected clock source can be further divided by 2, 3, 4, 5, 6, 7,
or 8 using the TBIDEX bits. The timer clock divider logic is reset when TBCLR is set.
NOTE:
Timer_B dividers
After programming ID or TBIDEX bits, set the TBCLR bit. This clears the contents of TBxR
and resets the clock divider logic to a defined state. The clock dividers are implemented as
down counters. Therefore, when the TBCLR bit is cleared, the timer clock immediately
begins clocking at the first rising edge of the Timer_B clock source selected with the
TBSSEL bits and continues clocking at the divider settings set by the ID and TBIDEX bits.
26.2.2 Starting the Timer
The timer may be started or restarted in the following ways:
•
The timer counts when MC > { 0 } and the clock source is active.
•
When the timer mode is either up or up/down, the timer may be stopped by loading 0 to TBxCL0. The
timer may then be restarted by loading a nonzero value to TBxCL0. In this scenario, the timer starts
incrementing in the up direction from zero.