Instruction Set Description
205
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
CPUX
4.6.2.45 SETZ
* SETZ
Set zero bit
Syntax
SETZ
Operation
1
→
N
Emulation
BIS #2,SR
Description
The zero bit (Z) is set.
Status Bits
N:
Not affected
Z:
Set
C:
Not affected
V:
Not affected
Mode Bits
OSCOFF, CPUOFF, and GIE are not affected.