SAPH and SAPH_A Registers
557
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Sequencer for Acquisition, Programmable Pulse Generator, and Physical
Interface (SAPH, SAPH_A)
21.8.35 SAPHAPLEV /SAPH_AAPLEV Register (Offset = 68h) [reset = 0h]
SAPHAPLEV/SAPH_AAPLEV is shown in
and described in
Return to
The PPG output level at pause when ASQ is controlling the measurement.
Figure 21-55. SAPHAPLEV/SAPH_AAPLEV Register
15
14
13
12
11
10
9
8
RESERVED
R/W-0h
7
6
5
4
3
2
1
0
RESERVED
PCPLEV
R/W-0h
R/W-0h
Table 21-40. SAPHAPLEV/SAPH_AAPLEV Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
RESERVED
R/W
0h
3-0
PCPLEV
R/W
0h
Bit 0 defines the PPG output level at pause for the first measurement
when PCPHIZ bit 0 = 0.
Bit 1 defines the PPG output level at pause for the second
measurement when PCPHIZ bit 1 = 0.
Bit 2 defines the PPG output level at pause for the third
measurement when PCPHIZ bit 2 = 0.
Bit 3 defines the PPG output level at pause for the fourth
measurement when PCPHIZ bit 3 = 0.
0 = Logical Low.
1 = Logical High.
Reset type: PUC