Timer_B Registers
688
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Timer_B
26.3.6 TBxEX0 Register
Timer_B x Expansion Register 0
(1)
After programming TBIDEX bits and configuration of the timer, set TBCLR bit to ensure proper reset of the timer divider logic.
Figure 26-21. TBxEX0 Register
15
14
13
12
11
10
9
8
Reserved
r0
r0
r0
r0
r0
r0
r0
r0
7
6
5
4
3
2
1
0
Reserved
TBIDEX
(1)
r0
r0
r0
r0
r0
rw-(0)
rw-(0)
rw-(0)
Table 26-11. TBxEX0 Register Description
Bit
Field
Type
Reset
Description
15-3
Reserved
R
0h
Reserved. Always reads as 0.
2-0
TBIDEX
RW
0h
Input divider expansion. These bits along with the ID bits select the divider for
the input clock.
000b = Divide by 1
001b = Divide by 2
010b = Divide by 3
011b = Divide by 4
100b = Divide by 5
101b = Divide by 6
110b = Divide by 7
111b = Divide by 8