eUSCI_B I2C Registers
844
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Enhanced Universal Serial Communication Interface (eUSCI) – I
2
C Mode
32.4 eUSCI_B I2C Registers
The eUSCI_B registers applicable in I
2
C mode and their address offsets are listed in
. The base
address can be found in the device-specific data sheet.
Table 32-3. eUSCI_B Registers
Offset
Acronym
Register Name
Type
Access
Reset
Section
00h
UCBxCTLW0
eUSCI_Bx Control Word 0
Read/write
Word
01C1h
00h
UCBxCTL1
eUSCI_Bx Control 1
Read/write
Byte
C1h
01h
UCBxCTL0
eUSCI_Bx Control 0
Read/write
Byte
01h
02h
UCBxCTLW1
eUSCI_Bx Control Word 1
Read/write
Word
0000h
06h
UCBxBRW
eUSCI_Bx Bit Rate Control Word
Read/write
Word
0000h
06h
UCBxBR0
eUSCI_Bx Bit Rate Control 0
Read/write
Byte
00h
07h
UCBxBR1
eUSCI_Bx Bit Rate Control 1
Read/write
Byte
00h
08h
UCBxSTATW
eUSCI_Bx Status Word
Read
Word
0000h
08h
UCBxSTAT
eUSCI_Bx Status
Read
Byte
00h
09h
UCBxBCNT
eUSCI_Bx Byte Counter Register
Read
Byte
00h
0Ah
UCBxTBCNT
eUSCI_Bx Byte Counter Threshold
Register
Read/Write
Word
00h
0Ch
UCBxRXBUF
eUSCI_Bx Receive Buffer
Read/write
Word
00h
0Eh
UCBxTXBUF
eUSCI_Bx Transmit Buffer
Read/write
Word
00h
14h
UCBxI2COA0
eUSCI_Bx I2C Own Address 0
Read/write
Word
0000h
16h
UCBxI2COA1
eUSCI_Bx I2C Own Address 1
Read/write
Word
0000h
18h
UCBxI2COA2
eUSCI_Bx I2C Own Address 2
Read/write
Word
0000h
1Ah
UCBxI2COA3
eUSCI_Bx I2C Own Address 3
Read/write
Word
0000h
1Ch
UCBxADDRX
eUSCI_Bx Received Address Register
Read
Word
1Eh
UCBxADDMASK
eUSCI_Bx Address Mask Register
Read/write
Word
03FFh
20h
UCBxI2CSA
eUSCI_Bx I2C Slave Address
Read/write
Word
0000h
2Ah
UCBxIE
eUSCI_Bx Interrupt Enable
Read/write
Word
0000h
2Ch
UCBxIFG
eUSCI_Bx Interrupt Flag
Read/write
Word
0002h
2Eh
UCBxIV
eUSCI_Bx Interrupt Vector
Read
Word
0000h