PMM Registers
89
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Power Management Module (PMM) and Supply Voltage Supervisor (SVS)
2.3.1 PMMCTL0 Register (offset = 00h) [reset = 9640h]
Power Management Module Control Register 0
Figure 2-4. PMMCTL0 Register
15
14
13
12
11
10
9
8
PMMPW
rw-1
rw-0
rw-0
rw-1
rw-0
rw-1
rw-1
rw-0
7
6
5
4
3
2
1
0
Reserved
SVSHE
Reserved
PMMREGOFF
PMMSWPOR
PMMSWBOR
Reserved
rw-[0]
rw-[1]
r0
rw-[0]
rw-(0)
rw-[0]
r0
r0
Table 2-2. PMMCTL0 Register Description
Bit
Field
Type
Reset
Description
15-8
PMMPW
RW
96h
PMM password. Always reads as 096h. Must be written with 0A5h to unlock the
PMM registers.
7
Reserved
RW
0h
Reserved. Must be written with 0.
6
SVSHE
RW
1h
High-side SVS enable.
0b = High-side SVS (SVSH) is disabled in LPM2, LPM3, LPM4, LPM3.5, and
LPM4.5. SVSH is always enabled in active mode, LPM0, and LPM1.
1b = SVSH is always enabled.
5
Reserved
R
0h
Reserved. Always reads as 0.
4
PMMREGOFF
RW
0h
Regulator off
0b = Regulator remains on when going into LPM3 or LPM4
1b = Regulator is turned off when going to LPM3 or LPM4. System enters
LPM3.5 or LPM4.5, respectively.
3
PMMSWPOR
RW
0h
Software POR. Setting this bit to 1 triggers a POR. This bit is self clearing.
0b = Normal operation
1b = Set to 1 to trigger a POR
2
PMMSWBOR
RW
0h
Software brownout reset. Setting this bit to 1 triggers a BOR. This bit is self
clearing.
0b = Normal operation
1b = Set to 1 to trigger a BOR
1-0
Reserved
R
0h
Reserved. Always reads as 0.