DAC Output Voltage
Input Voltage
ESIOUT1
Time
ESIDAC1R2
ESIDAC1R3
ESI Operation
973
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Extended Scan Interface (ESI)
The comparator and the DAC in both analog front-ends AFE1 and AFE2 are turned on and off by
ESICA(tsm) signal and the ESIDAC(tsm) signal. In case, the AFE1's comparator or DAC are not needed
they can be disabled by clearing the ESICA(tsm) and ESIDAC(tsm) control bits within ESITSM0 register.
AFE2 is disabled when its comparator and DAC are disabled. This can be done by clearing the
ESICA2EN and ESIDAC2EN bits. In case these bits are set the AFE2's comparator and DAC will be
controlled by the ESICA(tsm) and ESIDAC(tsm) control bits.
For each input there are two DAC registers to set the reference level as listed in
. Together with
the last stored output of the comparator, ESIOUTx, the two levels can be used as an analog hysteresis as
shown in
. The individual settings for the four inputs can be used to compensate for
mismatches between the sensors.
Table 37-3. Selected DAC Registers
Analog Front-
End
Selected Output Bit, ESIOUTx
Last Value of
ESIOUTx
DAC Register Used
AFE1
ESIOUT0
0
ESIDAC1R0
1
ESIDAC1R1
ESIOUT1
0
ESIDAC1R2
1
ESIDAC1R3
ESIOUT2
0
ESIDAC1R4
1
ESIDAC1R5
ESIOUT3
0
ESIDAC1R6
1
ESIDAC1R7
AFE2
ESIOUT4
0
ESIDAC2R0
1
ESIDAC2R1
ESIOUT5
0
ESIDAC2R2
1
ESIDAC2R3
ESIOUT6
0
ESIDAC2R4
1
ESIDAC2R5
ESIOUT7
0
ESIDAC2R6
1
ESIDAC2R7
Figure 37-7. Analog Hysteresis With DAC Registers
When TESTDX = 1, the ESIDAC1R6 and ESIDAC1R7 registers are used as the comparator reference as
described in
. Note that this feature is only available in AFE1.