Clock System Operation
96
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Clock System (CS) Module
3.2
Clock System Operation
After PUC, the CS module default configuration is:
•
LFXT is selected as the oscillator source for LFXTCLK. LFXTCLK is selected for ACLK (SELAx = 0)
and ACLK is undivided (DIVAx = 0).
•
DCOCLK is selected for MCLK and SMCLK (SELMx = SELSx = 3) and each are divided by 8
(DIVMx = DIVSx = 3).
•
LFXIN and LFXOUT pins are set to general-purpose I/Os and LFXT remains disabled until the I/O
ports are configured for LFXT operation.
•
HFXIN and HFXOUT pins are set to general-purpose I/Os and HFXT is disabled.
As previously stated, LFXT is selected by default, but LFXT is disabled. The crystal pins (LFXIN,
LFXOUT) are shared with general-purpose I/Os. To enable LFXT, the PSEL bits associated with the
crystal pins must be set. When a 32768-Hz crystal is used for LFXTCLK, the fault control logic
immediately causes ACLK to be sourced by LFMODCLK, and MCLK and SMCLK to be sourced by
MODCLK, because LFXT is not stable immediately (see
).
Status register control bits (SCG0, SCG1, OSCOFF, and CPUOFF) configure the MCU operating modes
and enable or disable portions of the clock system module (see the
System Resets, Interrupts, and
Operating Modes
chapter). Registers CSCTL0 to CSCTL6 configure the CS module.
The CS module can be configured or reconfigured by software at any time during program execution. The
CS control registers are password protected to prevent inadvertent access.
3.2.1 CS Module Features for Low-Power Applications
Conflicting requirements typically exist in battery-powered applications:
•
Low clock frequency for energy conservation and time keeping
•
High clock frequency for fast response times and fast burst processing capabilities
•
Clock stability over operating temperature and supply voltage
•
Low-cost applications with less-constrained clock accuracy requirements
The CS module addresses these conflicting requirements by allowing the user to select from the three
available clock signals: ACLK, MCLK, and SMCLK. A flexible clock distribution and divider system is
provided to fine tune the individual clock requirements.
3.2.2 LFXT Oscillator
The LFXT oscillator supports ultra-low-current consumption using a 32768-Hz watch crystal. A watch
crystal connects to LFXIN and LFXOUT and requires external capacitors on both terminals. These
capacitors should be sized according to the crystal or resonator specifications. Different crystal or
resonator ranges are supported by LFXT by choosing the proper LFXTDRIVE settings.
The LFXT pins are shared with general-purpose I/O ports. At power up, the LFXT clock defaults to "on"
and is the source for ACLK. However, at power-up the LFXT pins default to general-purpose I/O mode,
therefore, the LFXT clock remains disabled until the pins associated with LFXT are configured for LFXT
operation. The configuration of the shared I/O is determined by the PSEL bit associated with LFXIN and
the LFXTBYPASS bit. Setting the PSEL bit causes the LFXIN and LFXOUT ports to be configured for
LFXT operation. If LFXTBYPASS is also set, LFXT is configured for bypass mode of operation, and the
oscillator that is associated with LFXT is powered down. In bypass mode of operation, LFXIN can accept
an external square-wave clock input signal, and LFXOUT is configured as a general-purpose I/O. The
PSEL bit associated with LFXOUT is a don't care.
If the PSEL bit associated with LFXIN is cleared, both LFXIN and LFXOUT ports are configured as
general-purpose I/Os, and LFXT is disabled.
LFXT is enabled under any of the following conditions:
•
LFXT is a source for ACLK (SELAx = 0) and in active mode (AM) through LPM3 (OSCOFF = 0)
•
LFXT is a source for MCLK (SELMx = 0) and in active mode (AM) (CPUOFF = 0)
•
LFXT is a source for SMCLK (SELSx = 0) and in active mode (AM) through LPM1 (SMCLKOFF = 0)