DV
CC
Voltage
V
CORE
SVS
H_IT+
Time
BOR
Reset from SVS
H
PMM Operation
86
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Power Management Module (PMM) and Supply Voltage Supervisor (SVS)
2.2.3 Supply Voltage Supervisor - Power-Up
When the device is powering up, the SVSH function is enabled by default. Initially, DV
CC
is low, and
therefore the PMM holds the device in BOR reset. When the SVSH level is met, after a short delay the
BOR reset is released.
shows this process.
Figure 2-3. PMM Action at Device Power-Up
2.2.4 LPM3.5 and LPM4.5
LPM3.5 and LPM4.5 are additional low-power modes in which the core voltage regulator of the PMM is
completely disabled, providing additional power savings. Because there is no power supplied to V
CORE
during LPMx.5, the CPU and all digital modules including RAM are unpowered. This essentially disables
the entire device and thus the contents of the registers and RAM are lost. Any essential values should be
stored to FRAM before entering LPMx.5.
To enable LPMx.5 the PMMREGOFF bit in the PMMCTL0 register must be set.
The LOCKLPM5 bit in the PM5CTL0 register locks the I/O configuration and other LPMx.5 relevant
configurations after a wakeup from LPMx.5 until all the registers are configured again.
LPM3.5 and LPM4.5 can be configured with active SVS (SVSHE = 1) or with SVS disabled (SVSHE = 0).
Disabling the SVS results in lower power consumption, whereas enabling it provides the ability to detect
supply drops and getting a "wake-up" due to the supply drop below the SVS threshold. Note, the "wake-
up" due to a supply failure would not be flagged as a LPMx.5 wake-up but as a SVS reset event. In
LPM4.5 enabling the SVS results additionally in an about 4 times faster start-up time than with disabled
SVS.
Refer to
for complete descriptions and uses of LPMx.5.
NOTE:
In watchdog mode, the WDT_A prevents LPMx.5. Refer to
.
2.2.5 Brownout Reset (BOR)
The primary function of the brownout reset (BOR) circuit occurs when the device is powering up. It is
functional very early in the power-up ramp, generating a BOR that initializes the system. It also functions
when no SVS is enabled and a brownout condition occurs. It sustains this reset until the input power is
sufficient for the logic, for proper reset of the system.