12778474-002-2 Revision F – March 2004
TSG-3800 User’s Guide 163
Input Modules
Three-Port Input Module
The three-channel version of this module contains six counters to monitor the phase
of the input signals with respect to the system clocks. Phase measurements have a
resolution of 1 nanosecond and accuracy of 5 nanoseconds or better with a sample
rate of 20 per second. The one second averaged phase reading and the MTIE
measurements are reported to the CPU module each second. TDEV and MTIE
calculations are performed on the 20 samples per second measurements and
results presented to the CPU module when requested. The module configuration for
each input of framed or clock, frequency, and termination can be set and read using
software commands. Any mismatch between input signal and module configuration
is detected and reported when possible.
The module uses a micro-controller to make the measurements, perform the
calculations, and interface to the unit CPU through dual port RAM (memory). The
phase measurements are read and stored from six counters, 3 inputs in contrast
with 2 clocks, 20 times each second. The one second averages for each
measurement are computed and stored for transfer to the CPU each second. The
minimum and maximum phase reading for MTIE and the TDEV calculations are
also stored for the 20 samples each second for the three inputs against the selected
clock. This data can be retrieved by the CPU to provide MTIE and TDEV results
over any portion of the previous 24 hours of continuous operation.
The micro-controller performs power-up self tests on the module to verify correct
operation and configures the input circuits to the setup stored in the non-volatile
RAM. The setup information identifies each expected input as a framed or clock
signal, frequency, termination, framing format, zero suppression mode, and CRC
checking. If the module is replacing a same type, the setup information is updated
by the CPU, else the setup is transferred to the CPU. The module provides the
module Item Number (I/N), Serial Number (S/N), and Firmware (F/W) Rev to the
CPU. For framed input signals the micro-controller monitors for LOS, AIS, OOF,
BPV, and CRC errors each second and reads the SSM if available. For clock
signals the input is checked for LOS and a valid frequency. The micro-controller also
operates the front panel LED indicators to provide a visual status indication. A
watchdog timer circuit provides detection of improper micro-controller operation.
This module gets power from the main shelf, Power A and B. These redundant
sources of –48 vDC are diode coupled and fused, allowing it to draw power from
either source. The internal fuse labeled F1, protects the circuitry from excessive
current. The DC-to-DC Converter changes the negative voltage into +5 vDC and the
green POWER LED on the front panel indicates power is available to the module.
The POWER indicator turns off in the event of any loss of power, such as the fuse
on the module opens, loss of both –48 vDC power inputs, or if the regulator fails.
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