Renesas V850 Series, Руководство пользователя, Страница: 756 / 1556

R01UH0336EJ0102 Rev.1.02 Page 756 of 1538
Jul 17, 2014
V850E2/PG4-L Section 15 TSG2 (TSG20)
(23) TSG2n Compare Register 3, 4 (TSnCMP3W)
This register specifies the compare value.
Access This register can be read/written in 32-bit units.
Address <
TSG2n_base1
> + 04C
H
Initial value 00000000
H
This register is initialized by a reset from any source.
Note The dead time function is enabled in all operating modes.
In 120-DC mode, the output from TSG2nO1 to TSG2nO6 is controlled by
TSnCMPm, TSnPAT0, and TSnPAT1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TSnCMP4 (16-bit compare register)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSnCMP3 (16-bit compare register)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 15-29 TSnCMP3W Register Setting
Operating Mode TSnCMP3 TSnCMP4 Minimum Value Maximum Value
PWM mode TSG2nO2 clear
timing TSG2nO2 set timing 0000
H
T 1
(TSnCMP0 <
FFFF
H
) or FFFF
H
HT-PWM mode - - - -
SP-PWM mode - - - -
120-DC mode Duty when
TSG2nO2,
TSG2nO4, or
TSG2nO6 output
pattern is selected
by TSnPAT1 Duty when
TSG2nO2,
TSG2nO4, or
TSG2nO6 output
pattern is selected
by TSnPAT1 0000
H
T 1
(TSnCMP0 <
FFFF
H
) or FFFF
H