Renesas V850 Series, Руководство пользователя

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R01UH0336EJ0102 Rev.1.02 Page 1405 of 1538
Jul 17, 2014
V850E2/PG4-L Section 24 Peripheral Interconnection (PIC)
Note 1. Change the set value depending on the system used.
Note 2. For dead time control, an even numbered CH and an odd numbered CH are
used as a pair to output the positive and negative phase waveforms. For
details, refer to Section 13, Timer Array Unit B (TAUB).
Registers related to TAUB0 channels in common (cont.)
Function Register Bit Position Bit Name Set Value Note
TAUB0 TAUB0TOL
15 TOL15 1 *
1
Negative logic output (active low)
14 TOL14 Don’t care
13 TOL13 1 *
1
Negative logic output (active low)
12 TOL14 Don’t care
11 TOL11 1 *
1
Negative logic output (active low)
10 TOL10 Don’t care
9 to 4 TOL09 to
TOL04 0 *
1
Positive logic output (active high)
3 TOL03 Don’t care
2 TOL02 0 Positive logic output (active high)
1, 0 TOL01
TOL00 Don’t care
TAUB0TDE 15 to 10 TDE15 to
TDE10 0 Dead time control is disabled.
9 to 4 TDE09 to
TDE04 1 Dead time control is abled.
3 TDE03 Don’t care
2 TDE02 0 Dead time control is disabled.
1, 0 TDE01
TDE00 Don’t care
TAUB0TDL 15 to 10 TDL15 to
TDL10 0 Invalid since dead time control is disabled.
9 TDL09 1 Operates for negative phase of W phase.
8 TDL08 0 *
1
Operates for positive phase of W phase.
7 TDL07 1 *
1
Operates for negative phase of V phase.
6 TDL06 0 *
1
Operates for positive phase of V phase.
5 TDL05 1 *
1
Operates for negative phase of U phase.
4 TDL04 0 *
1
Operates for positive phase of U phase.
3 TDL03 Don’t care
2 TDL02 0 Invalid since dead time control is disabled.
1, 0 TDL01
TDL00 Don’t care