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48
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6 F 2 S 0 8 4 6
In this system, the transmitted signal is a trip block signal, and transmission of that signal is
required only in the case of external faults. Therefore, even if power line carrier is used, a failure to
operate or false operation due to attenuation of the signal would not be experienced.
If the modulation method of the telecommunication circuits is a frequency shift method,
frequencies f1 and f2 are assigned to the trip block signal and trip permission signal, respectively.
The receive end recognizes signals CR1 and CR2 as corresponding to respective frequencies as
the actual trip permission signals when either one of the following conditions is established and
executes tripping on condition that the overreaching element should operate.
•
CR1 is lost and only CR2 is received.
•
Both CR1 and CR2 are lost.
The latter is also applicable if there is a telecommunication circuit failure in addition to attenuation
of the signal at the fault point. Therefore, when the latter condition continues for a certain period
or longer, the UOP is blocked and a telecommunication circuit failure alarm is output.
The UOP is provided with an echo function and weak infeed trip function and even when applied
to a line with open terminals or weak infeed terminals, it allows fast tripping of both terminals for
any fault along the whole length of the protected line. An undervoltage element UVL is provided
for weak infeed tripping. (See Section 2.4.3.5 for protection for weak infeed terminal.)
When a sequential fault clearance occurs for a fault on a parallel line, the direction of the current
on the healthy line is reversed. The status of the forward overreaching element changes from an
operating to a reset state at the terminal where the current is reversed from an inward to an outward
direction, and from a non-operating status to an operating status at the other terminal. In this
process, if the operating periods of the forward overreaching element of both terminals overlap,
the healthy line may be tripped erroneously. To prevent this, current reversal logic is provided.
(See Section 2.4.3.6 for current reversal.)
For the communication channel, a single channel shared by different terminals or multiplex
channels, one channel for each direction can be used.
Scheme Logic
Figure 2.4.3.3 shows the scheme logic of the UOP. The logic level of transmit signal CS and
receive signal R1-CR is "1" for a trip block signal and "0" for a trip permission signal.
The UOP changes its transmit signal CS from a trip block signal to trip permission signal under
one of the following conditions. The logic level of CS changes from 1 to 0.
•
The forward overreaching zone 2 or zone 3 selected by the scheme switch [ZONESEL]
operates and the current reversal logic (CRL) is not picked up. If the PLC signal
PSCM_TCHDEN is established, the delayed pick-up timer TCHD is provided.
•
The circuit breaker is open and the trip permission signal (R1-CR=0) is received from
the other terminal.
•
The forward overreaching zone 2 or zone 3 and reverse looking Z4 are not operating and
a trip permission signal is received from the other terminal.
The last two are implemented when an echo function (ECH) is selected. (Refer to Section 2.4.3.5
for echo function.)
Transmission of a trip permission signal continues for the TSBCT setting even after the local
terminal is tripped. This is to ensure that command tripping is executed at the remote terminal.
The UOP outputs single-phase tripping signal S-TRIP or three-phase tripping signal M-TRIP to
the local terminal when the trip permission signal (R1-CR=0) is received from the remote
terminal, the current reversal logic (CRL) is not picked up and one of the following conditions is
established.
Summary of Contents for GRZ100 B Series
Page 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Page 271: ... 270 6 F 2 S 0 8 4 6 ...
Page 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Page 307: ... 306 6 F 2 S 0 8 4 6 ...
Page 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Page 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Page 321: ... 320 6 F 2 S 0 8 4 6 ...
Page 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Page 331: ... 330 6 F 2 S 0 8 4 6 ...
Page 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Page 377: ... 376 6 F 2 S 0 8 4 6 ...
Page 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Page 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 389: ... 388 6 F 2 S 0 8 4 6 ...
Page 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Page 401: ... 400 6 F 2 S 0 8 4 6 ...
Page 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Page 405: ... 404 6 F 2 S 0 8 4 6 ...
Page 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Page 417: ... 416 6 F 2 S 0 8 4 6 ...
Page 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Page 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Page 437: ... 436 6 F 2 S 0 8 4 6 ...
Page 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Page 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Page 447: ......