⎯
123
⎯
6 F 2 S 0 8 4 6
As shown in the figure, if an evolving fault occurs before TEVLV is picked up, three-phase
tripping is performed. If this occurs, TSPR and TEVLV are reset, and TTPR1 is now started.
After TTPR1 is picked up, three-phase reclosing is performed based on the status of the voltage
and synchronism check elements output signal SYN-OP. If an evolving fault occurs after the
TEVLV has picked up, autoreclose is reset and reclosing is not performed.
Voltage and synchronism check
There are four voltage modes as shown below when all three phases of the circuit breaker are
opened. The voltage and synchronism check is applicable to voltage modes 1 to 3 and controls the
energizing process of the lines and busbars in the three-phase autoreclose mode.
Voltage
Mode
1 2 3 4
Busbar voltage (VB)
live live dead
dead
Line voltage (VL)
live dead
live dead
The synchronism check is performed for voltage mode 1 while the voltage check is performed for
voltage modes 2 and 3.
Figure 2.6.2.3 Energizing Control Scheme
Figure 2.6.2.3 shows the energizing control scheme. The voltage and synchronism check output
signal SYN-OP is generated when the following conditions have been established;
•
Synchronism check element SYN1 operates and on-delay timer TSYN1 is picked up.
•
Busbar overvoltage detector OVB and line undervoltage detector UVL1 operate, and on-delay
timer TLBD1 is picked up. (This detects live bus and dead line condition.)
•
Busbar undervoltage detector UVB and line overvoltage detector OVL1 operate, and on-delay
timer TDBL1 is picked up. (This detects dead bus and live line condition.)
Using the scheme switch [VCHK], the energizing direction can be selected.
&
SYN1
UVL1
OVL1
OVB
&
UVB
+
"
OFF
"
[VCHK]
"
SY
"
"
DB
"
"
LB
"
DBLL
LBDL
SYN-OP
TLBD1
0.01 – 10.00S
0.01 – 1.00S
TDBL1
0.01 – 1.00S
&
&
TSYN1
≥
1
86
87
90
88
89
273
T3PLL
0.01 – 1.00S
397
3PLL
(Three phase live line)
Summary of Contents for GRZ100 B Series
Page 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Page 271: ... 270 6 F 2 S 0 8 4 6 ...
Page 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Page 307: ... 306 6 F 2 S 0 8 4 6 ...
Page 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Page 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Page 321: ... 320 6 F 2 S 0 8 4 6 ...
Page 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Page 331: ... 330 6 F 2 S 0 8 4 6 ...
Page 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Page 377: ... 376 6 F 2 S 0 8 4 6 ...
Page 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Page 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 389: ... 388 6 F 2 S 0 8 4 6 ...
Page 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Page 401: ... 400 6 F 2 S 0 8 4 6 ...
Page 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Page 405: ... 404 6 F 2 S 0 8 4 6 ...
Page 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Page 417: ... 416 6 F 2 S 0 8 4 6 ...
Page 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Page 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Page 437: ... 436 6 F 2 S 0 8 4 6 ...
Page 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Page 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Page 447: ......