
⎯
74
⎯
6 F 2 S 0 8 4 6
2.4.9 Overvoltage and Undervoltage Protection
2.4.9.1 Overvoltage Protection
GRZ100 provides four independent overvoltage elements with programmable
dropoff/pickup(DO/PU) ratio for phase-to-phase voltage input and phase voltage input. OVS1 and
OVS2 are used for phase-to-phase voltage input, and OVG1 and OVG2 for phase voltage input.
OVS1 and OVG1 are programmable for inverse time (IDMT) or definite time (DT) operation.
OVS2 and OVG2 have definite time characteristic only.
The OVS1 and OVG1 overvoltage protection elements have an IDMT characteristic defined by
equation (1):
( )
⎥
⎥
⎥
⎦
⎤
⎢
⎢
⎢
⎣
⎡
−
×
=
1
1
Vs
V
TMS
t
(1)
where:
t = operating time for constant voltage V (seconds),
V = energising voltage (V),
Vs = overvoltage setting (V),
TMS = time multiplier setting.
The IDMT characteristic is illustrated in Figure 2.4.9.1.
The OVS2 and OVG2 elements are used for definite time overvoltage protection.
Definite time reset
The definite time resetting characteristic is applied to the OVS1 and OVG1 elements when the
inverse time delay is used.
If definite time resetting is selected, and the delay period is set to instantaneous, then no
intentional delay is added. As soon as the energising voltage falls below the reset threshold, the
element returns to its reset condition.
If the delay period is set to some value in seconds, then an intentional delay is added to the reset
period. If the energising voltage exceeds the setting for a transient period without causing tripping,
then resetting is delayed for a user-definable period. When the energising voltage falls below the
reset threshold, the integral state (the point towards operation that it has travelled) of the timing
function (IDMT) is held for that period.
This does not apply following a trip operation, in which case resetting is always instantaneous.
Overvoltage elements OVS1, OVS2, OVG1 and OVG2 have a programmable dropoff/pickup
(DO/PU) ratio.
Summary of Contents for GRZ100 B Series
Page 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Page 271: ... 270 6 F 2 S 0 8 4 6 ...
Page 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Page 307: ... 306 6 F 2 S 0 8 4 6 ...
Page 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Page 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Page 321: ... 320 6 F 2 S 0 8 4 6 ...
Page 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Page 331: ... 330 6 F 2 S 0 8 4 6 ...
Page 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Page 377: ... 376 6 F 2 S 0 8 4 6 ...
Page 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Page 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 389: ... 388 6 F 2 S 0 8 4 6 ...
Page 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Page 401: ... 400 6 F 2 S 0 8 4 6 ...
Page 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Page 405: ... 404 6 F 2 S 0 8 4 6 ...
Page 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Page 417: ... 416 6 F 2 S 0 8 4 6 ...
Page 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Page 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Page 437: ... 436 6 F 2 S 0 8 4 6 ...
Page 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Page 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Page 447: ......