⎯
55
⎯
6 F 2 S 0 8 4 6
to the reclosing mode of the autoreclose function.
The weak infeed trip function can be disabled by the scheme switch [WKIT] and the PLC signal
WKIT_BLOCK.
2.4.3.6 Measure for Current Reversal
In response to faults on parallel lines, sequential opening of the circuit breaker may cause a fault
current reversal on healthy lines. This phenomenon may cause false operation of the POP, UOP
and BOP schemes in the worst case. To prevent this, the POP, UOP and BOP are provided with
current reversal logic.
With the parallel line arrangement as shown in Figure 2.4.3.7 (a), suppose that a fault occurs at
time t1 at point F of line L1, A1 trips at time t2 first and then B1 trips at time t3. The direction of
the current that flows in healthy line L2 can be reversed at time t2. That is, the current flows from
terminal B to terminal A as indicated by a solid line in the period from time t1 to t2, and from
terminal A to terminal B as indicated by a broken line in the period from time t2 to t3. This current
reversal phenomenon may occur with the presence of an external looped circuit if not for parallel
lines.
Figure 2.4.3.7 (b) shows a sequence diagram of Z3 and Z4 and the current reversal logic CRL on
healthy line L2 before and after the occurrence of a current reversal. When the current is reversed,
Z3 operation and Z4 reset are seen at terminal A, while reset of Z3 and operation of Z4 are seen at
terminal B. If at this time, Z3 of A2 operates before Z3 of B2 is reset, this may cause false
operation of the POP, UOP and BOP on line L2.
Figure 2.4.3.7 Current Reversal Phenomenon
Figure 2.4.3.8 shows the current reversal logic. The current reversal logic is picked up on
condition that reverse looking Z4 has operated and forward overreaching zone 2 or zone 3 have
not operated, and the output CRL immediately controls the send signal to a trip block signal and at
the same time blocks local tripping. If the condition above continues longer than 20ms, the output
A2
B2
B
A
A1 B1
F
L1
L2
(a) Direction of fault current
: Before A1 opened
: After A1 opened
t1
CRL
Z4
Z3
A2
(b) Sequence diagram
t2
t3
TREBK setting
TREBK setting
CRL
Z4
Z3
B2
Summary of Contents for GRZ100 B Series
Page 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Page 271: ... 270 6 F 2 S 0 8 4 6 ...
Page 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Page 307: ... 306 6 F 2 S 0 8 4 6 ...
Page 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Page 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Page 321: ... 320 6 F 2 S 0 8 4 6 ...
Page 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Page 331: ... 330 6 F 2 S 0 8 4 6 ...
Page 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Page 377: ... 376 6 F 2 S 0 8 4 6 ...
Page 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Page 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 389: ... 388 6 F 2 S 0 8 4 6 ...
Page 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Page 401: ... 400 6 F 2 S 0 8 4 6 ...
Page 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Page 405: ... 404 6 F 2 S 0 8 4 6 ...
Page 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Page 417: ... 416 6 F 2 S 0 8 4 6 ...
Page 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Page 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Page 437: ... 436 6 F 2 S 0 8 4 6 ...
Page 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Page 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Page 447: ......