⎯
66
⎯
6 F 2 S 0 8 4 6
[EFIBT], and also can be disabled by the binary input signals (PLC signals) OC_BLOCK,
OCI_BLOCK, EF_BLOCK and EFI_BLOCK. The EF element issues an alarm for the backup trip
for earth fault. The alarm can be disabled by the scheme switch [EFBTAL]. The OC and EF
protections can trip instantaneously by PLC signals OC_INST_TP and EF_INST_TP.
OC-A
≥
1
&
0.00 – 10.00s
TOC
t
0
t
0
t
0
"ON"
[OCBT]
+
1
OC_BLOCK
1625
&
&
&
"ON"
[OCIBT]
+
1
OCI_BLOCK
1626
&
&
OC-B_FS
1609
94
95
96
97
98
99
OC_TRIP
326
OC_INST_TP
1703
OC-A_FS
1608
OC-A TP
OC-B TP
OC-C TP
≥
1
≥
1
≥
1
OC_3PTP
1716
&
615
614
613
OC-A TRIP
OC-B TRIP
OC-C TRIP
≥
1
OCI_TRIP
327
OCI-A TP
OCI-B TP
OCI-C TP
≥
1
≥
1
≥
1
OCI_3PTP
1717
&
618
617
616
OCI-A TRIP
OCI-B TRIP
OCI-C TRIP
OC-B
OC-C
OCI-A
OCI-B
OCI-C
OC-C_FS
1610
&
&
&
≥
1
≥
1
≥
1
OCI-B_FS
1613
OCI-A_FS
1612
OCI-C_FS
1614
(M-TRIP)
S-TRIP
S-TRIP
BU-TRIP
≥
1
EF
TEF
t
0
0.00 – 10.00s
&
"ON"
[EFBT]
+
"ON"
[EFBTAL]
+
1
EF_BLOCK
1627
&
EFI
&
"NOD"
[DEFI]
+
1
EFI_BLOCK
1628
60
61
EF_BU-TRIP
EFI_TRIP
EF_ALARM
194
187
185
184
EF_INST_TP
1702
&
≥
1
≥
1
EF_TRIP
678
Figure 2.4.5.1 Overcurrent Backup Protection
2.4.5.1 Inverse Time Overcurrent Backup Protection
In a system in which the fault current is mostly determined by the fault location, without being
greatly affected by changes in the power source impedance, it is advantageous to use inverse
definite minimum time (IDMT) overcurrent protection. Reasonably fast tripping can be obtained
even at a terminal close to the power source by using inverse time characteristics. In the IDMT
overcurrent protection function, one of the following three IEC-standard-compliant inverse time
characteristics and one long time inverse characteristic is available.
Summary of Contents for GRZ100 B Series
Page 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Page 271: ... 270 6 F 2 S 0 8 4 6 ...
Page 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Page 307: ... 306 6 F 2 S 0 8 4 6 ...
Page 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Page 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Page 321: ... 320 6 F 2 S 0 8 4 6 ...
Page 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Page 331: ... 330 6 F 2 S 0 8 4 6 ...
Page 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Page 377: ... 376 6 F 2 S 0 8 4 6 ...
Page 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Page 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 389: ... 388 6 F 2 S 0 8 4 6 ...
Page 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Page 401: ... 400 6 F 2 S 0 8 4 6 ...
Page 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Page 405: ... 404 6 F 2 S 0 8 4 6 ...
Page 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Page 417: ... 416 6 F 2 S 0 8 4 6 ...
Page 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Page 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Page 437: ... 436 6 F 2 S 0 8 4 6 ...
Page 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Page 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Page 447: ......