⎯
78
⎯
6 F 2 S 0 8 4 6
Definite time reset
The definite time resetting characteristic is applied to the UVS1 and UVG1 elements when the
inverse time delay is used.
If definite time resetting is selected, and the delay period is set to instantaneous, then no
intentional delay is added. As soon as the energising voltage rises above the reset threshold, the
element returns to its reset condition.
If the delay period is set to some value in seconds, then an intentional delay is added to the reset
period. If the energising voltage is below the undercurrent setting for a transient period without
causing tripping, then resetting is delayed for a user-definable period. When the energising
voltage rises above the reset threshold, the integral state (the point towards operation that it has
travelled) of the timing function (IDMT) is held for that period.
This does not apply following a trip operation, in which case resetting is always instantaneous.
Undervoltage Inverse Time
Curves
1.000
10.000
100.000
1000.000
0
0.2
0.4
0.6
0.8
1
Applied Voltage (x Vs)
Op
e
ra
ti
n
g
T
im
e
(
sec
s)
TMS = 10
TMS = 5
TMS = 2
TMS = 1
Figure 2.4.9.6 IDMT Characteristic
Scheme Logic
Figures 2.4.9.7 and 2.4.9.9 show the scheme logic of the UVS1 and UVG1 undervoltage
protection with selective definite time or inverse time characteristic. The definite time protection
is selected by setting [UV
∗
1EN] to “DT”, and trip signal UV
∗
1_TRIP is given through the
delayed pick-up timer TU
∗
1. The inverse time protection is selected by setting [UV
∗
1EN] to
“IDMT”, and trip signal UV
∗
1_TRIP is given.
The UVS1 and UVG1 protections can be disabled by the scheme switch [UV
∗
1EN] or the PLC
signal UV
∗
1_BLOCK.
These protections are available to trip instantaneously by the PLC signal UV
∗
1_INST_TP except
for [UV
∗
1EN]=“OFF” setting.
Figures 2.4.9.8 and 2.4.9.10 show the scheme logic of the UVS2 and UVG2 protection with
Summary of Contents for GRZ100 B Series
Page 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Page 271: ... 270 6 F 2 S 0 8 4 6 ...
Page 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Page 307: ... 306 6 F 2 S 0 8 4 6 ...
Page 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Page 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Page 321: ... 320 6 F 2 S 0 8 4 6 ...
Page 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Page 331: ... 330 6 F 2 S 0 8 4 6 ...
Page 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Page 377: ... 376 6 F 2 S 0 8 4 6 ...
Page 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Page 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 389: ... 388 6 F 2 S 0 8 4 6 ...
Page 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Page 401: ... 400 6 F 2 S 0 8 4 6 ...
Page 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Page 405: ... 404 6 F 2 S 0 8 4 6 ...
Page 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Page 417: ... 416 6 F 2 S 0 8 4 6 ...
Page 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Page 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Page 437: ... 436 6 F 2 S 0 8 4 6 ...
Page 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Page 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Page 447: ......