⎯
52
⎯
6 F 2 S 0 8 4 6
UVC. The phase selection logic is described in Section 2.4.3.7.
&
&
≥
1
CS
Z4
20ms
t
0
0.00 – 10.00s
0
t
M-TRIP
S-TRIP
Phase
Selection
&
Z2
Z3
TCHD
0 - 50ms
t
0
"Z2"
"Z3"
[ZONESEL]
[PSB-CR]
" ON "
PSB
NON VTF
&
R1-CR
1
TREBK
TSBCT
0.00 – 1.00s
0 t
Figure 2.4.3.4 BOP Scheme Logic
Setting
The following shows the setting elements necessary for the BOP and their setting ranges.
For the settings of Z2, Z3 and UVC, refer to Section 2.4.1.
Element Range
Step Default Remarks
Z4S
0.01 - 50.00
Ω
0.01
Ω
8.00
Ω
Z4 reach
(0.1 – 250.0
Ω
0.1
Ω
40.0
Ω
) (*)
BRRS
0.10 - 20.00
Ω
0.01
Ω
5.10
Ω
Reverse right blinder reach
(0.5 - 100.0
Ω
0.1
Ω
25.5
Ω
)
Z4G
0.01 - 100.00
Ω
0.01
Ω
8.00
Ω
Z4 reach
(0.1 – 500.0
Ω
0.1
Ω
40.0
Ω
)
BRRG
0.10 - 20.00
Ω
0.01
Ω
5.10
Ω
Reverse right blinder reach
(0.5 - 100.0
Ω
0.1
Ω
25.5
Ω
)
TCHD
0 - 50 ms
1 ms
12 ms
Channel delay time
TREBK
0.00 - 10.00s
0.01s
0.10s
Current reversal block time
TSBCT
0.00 – 1.00s
0.01s
0.10s
PROTECTION
SCHEME
3ZONE/Z1EXT/PUP/POP/UOP/
BOP /POP+DEF/UOP+DEF/
BOP+DEF/PUP+DEF
POP Scheme
selection
ZONESEL
Z2/Z3
Z2
Overreaching element selection
PSB - CR
OFF/ON
ON
Power swing blocking
(*) Ohmic values shown in the parentheses are in the case of 1 A rating. Other ohmic values are in the
case of 5 A rating.
The following elements have fixed setting values or their settings are interlinked with other
elements listed above. So no setting operation is required.
Element Setting
Remarks
Z4BS
Fixed to 1.5
Ω
Z4 reverse offset reach
(Fixed to 7.5
Ω
) (*1)
Z4S
θ
(*2)
Interlinked with Z3S
θ
Characteristic angle of Z4 mho element
Z4BS
θ
(*3)
Interlinked with ZBS
θ
Angle of Z4 directional element
BRRS
θ
Fixed to 75°
Angle of reverse right blinder BRRS
BRLS
Interlinked with BRRS Reverse left blinder
BRLS
θ
Interlinked with BFLS
θ
Angle of reverse left blinder BRLS
Z4G
θ
(*2)
Interlinked with Z3G
θ
Characteristic angle of Z4 mho element
Summary of Contents for GRZ100 B Series
Page 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Page 271: ... 270 6 F 2 S 0 8 4 6 ...
Page 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Page 307: ... 306 6 F 2 S 0 8 4 6 ...
Page 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Page 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Page 321: ... 320 6 F 2 S 0 8 4 6 ...
Page 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Page 331: ... 330 6 F 2 S 0 8 4 6 ...
Page 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Page 377: ... 376 6 F 2 S 0 8 4 6 ...
Page 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Page 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 389: ... 388 6 F 2 S 0 8 4 6 ...
Page 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Page 401: ... 400 6 F 2 S 0 8 4 6 ...
Page 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Page 405: ... 404 6 F 2 S 0 8 4 6 ...
Page 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Page 417: ... 416 6 F 2 S 0 8 4 6 ...
Page 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Page 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Page 437: ... 436 6 F 2 S 0 8 4 6 ...
Page 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Page 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Page 447: ......