⎯
236
⎯
6 F 2 S 0 8 4 6
•
Adjust the magnitude of Va and Vb while retaining the conditions above and measure the
voltage Va at which the element operates.
•
The theoretical operating voltage is obtained by 2IT
×
Z
OST
when the setting reach is Z
OST
.
Check that the measured voltage is within
±
5% of the theoretical voltage value when it is
expressed with 2Va (= Va
−
Vb).
Element
ZOST
IT
2IT
×
ZOST Measured voltage (2V
a
)
OSTR2
6.5.1.3 Phase Selection Element UVC
The testing circuit is shown in Figure 6.5.1.2.
UVC elements and their output signal numbers are listed below.
Measuring element
Signal number
UVC-A 66
UVC-B 67
UVC-C 68
The following shows the case when testing UVC-A.
•
Press 5 (= Logic circuit) on the Test screen to display the Logic circuit screen.
•
Enter 66 as a signal number to be observed at monitoring jack A and press the ENTER key.
•
Apply a three-phase rated voltage.
•
Set the test current IT to zero ampere and adjust the voltage. Measure the voltage at which the
element operates. Check that the voltage is within
±
5% of the setting UVCV. (The default
setting of the UVCV is 48 V.)
•
Choose a test current IT by referring to the table below, which shows the relation of setting
reach UVCZ, test current IT and measuring error.
UVCZ IT
Error
0.0- 2.0
Ω
(0 - 10
Ω
10A
5A) (*)
±
5%
2.1 – 10.0
Ω
(11 - 50
Ω
5A
1A)
±
5%
10.1 – 20.0
Ω
(51 - 100
Ω
2.5A
0.5A)
±
5%
20.1 – 50.0
Ω
(101 - 250
Ω
1A
0.2A)
±
7%
(*) Values shown in parentheses are in the case of 1A rating. Other values are in the case of 5A
rating.
•
Set the test voltage and test current phase relation as shown below. That is, Va, Vb, and Vc are
balanced, and IT lags Va by UVC characteristic angle UVC
θ
.
(The default setting of UVC
θ
is 85°.)
Summary of Contents for GRZ100 B Series
Page 264: ... 263 6 F 2 S 0 8 4 6 Appendix A Block Diagram ...
Page 271: ... 270 6 F 2 S 0 8 4 6 ...
Page 272: ... 271 6 F 2 S 0 8 4 6 Appendix B Signal List ...
Page 307: ... 306 6 F 2 S 0 8 4 6 ...
Page 308: ... 307 6 F 2 S 0 8 4 6 Appendix C Variable Timer List ...
Page 310: ... 309 6 F 2 S 0 8 4 6 Appendix D Binary Input Output Default Setting List ...
Page 321: ... 320 6 F 2 S 0 8 4 6 ...
Page 322: ... 321 6 F 2 S 0 8 4 6 Appendix E Details of Relay Menu and LCD Button Operation ...
Page 331: ... 330 6 F 2 S 0 8 4 6 ...
Page 340: ... 339 6 F 2 S 0 8 4 6 Appendix G Typical External Connections ...
Page 377: ... 376 6 F 2 S 0 8 4 6 ...
Page 384: ... 383 6 F 2 S 0 8 4 6 Appendix J Return Repair Form ...
Page 388: ... 387 6 F 2 S 0 8 4 6 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 389: ... 388 6 F 2 S 0 8 4 6 ...
Page 390: ... 389 6 F 2 S 0 8 4 6 Appendix K Technical Data ...
Page 401: ... 400 6 F 2 S 0 8 4 6 ...
Page 402: ... 401 6 F 2 S 0 8 4 6 Appendix L Symbols Used in Scheme Logic ...
Page 405: ... 404 6 F 2 S 0 8 4 6 ...
Page 406: ... 405 6 F 2 S 0 8 4 6 Appendix M Example of Setting Calculation ...
Page 417: ... 416 6 F 2 S 0 8 4 6 ...
Page 418: ... 417 6 F 2 S 0 8 4 6 Appendix N IEC60870 5 103 Interoperability and Troubleshooting ...
Page 434: ... 433 6 F 2 S 0 8 4 6 Appendix P Inverse Time Characteristics ...
Page 437: ... 436 6 F 2 S 0 8 4 6 ...
Page 438: ... 437 6 F 2 S 0 8 4 6 Appendix Q Failed Module Tracing and Replacement ...
Page 444: ... 443 6 F 2 S 0 8 4 6 Appendix R Ordering ...
Page 447: ......