ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 103 -
Revision 2.4
5.2.8
System Control Registers
Key control and status features of Coterx-M0 are managed centrally in a System Control Block within
the System Control Registers.
For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical
Reference Manual” and “ARM® v6-M Architecture Reference Manual”
.
R
: read only,
W
: write only,
R/W
: both read and write,
W&C
: Write 1 clear
Register
Offset
R/W
Description
Reset Value
SYSINFO Base Address:
SYSINFO_BA = 0xE000_ED00
SYSINFO_CPUID
SYS0x000
R
CPUID Base Register
0x410C_C200
SYSINFO_ICSR
SYS0x004
R/W
Interrupt Control State Register
0x0000_0000
SYSINFO_AIRCTL
SYS0x00C
R/W
Application Interrupt and Reset Control Register
0xFA05_0000
SYSINFO_SCR
SYS0x010
R/W
System Control Register
0x0000_0000
SYSINFO_SHPR2
SYS0x01C
R/W
System Handler Priority Register 2
0x0000_0000
SYSINFO_SHPR3
SYS0x020
R/W
System Handler Priority Register 3
0x0000_0000
Note: In BSP register structure, the prefix is structure name, and register will be no prefix, for example
SYSINFO_ is the prefix, SYSINFO_SHPR3 will be SYSINFO->SHPR3