ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 323 -
Revision 2.4
I2S Interrupt Enable Register (I2S_IEN)
Register
Offset
R/W
Description
Reset Value
I2S_IEN
0x08
R/W
I2S Interrupt Enable Register
0x0000_0000
15
14
13
12
11
10
9
8
Reserved
LZCIEN
RZCIEN
TXTHIEN
TXOVIEN
TXUDIEN
7
6
5
4
3
2
1
0
Reserved
RXTHIEN
RXOVIEN
RXUDIEN
Table 5-134 I2S Interrupt Enable Register (I2S_IEN, address 0x400A_0008)
Bits
Description
[31:13]
Reserved
Reserved.
[12]
LZCIEN
Left Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and left channel has zero cross event
0 = Disable interrupt.
1 = Enable interrupt.
[11]
RZCIEN
Right Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and right channel has zero cross event
0 = Disable interrupt.
1 = Enable interrupt.
[10]
TXTHIEN
Transmit FIFO Threshold Level Interrupt Enable
Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than
TXTH[2:0].
0 = Disable interrupt.
1 = Enable interrupt.
[9]
TXOVIEN
Transmit FIFO Overflow Interrupt Enable
Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1
0 = Disable interrupt.
1 = Enable interrupt.
[8]
TXUDIEN
Transmit FIFO Underflow Interrupt Enable
Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.
0 = Disable interrupt.
1 = Enable interrupt.
[7:3]
Reserved
Reserved.
[2]
RXTHIEN
Receive FIFO Threshold Level Interrupt
Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or
equal to RXTH[2:0].
0 = Disable interrupt.
1 = Enable interrupt.
[1]
RXOVIEN
Receive FIFO Overflow Interrupt Enable
0 = Disable interrupt.
1 = Enable interrupt.
