ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 237 -
Revision 2.4
[7:4]
SUSPITV
Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive
transmit/receive transactions in a transfer. The definition of the suspend interval is
the interval between the last clock edge of the preceding transaction word and the
first clock edge of the following transaction word. The default value is 0x3. The
period of the suspend interval is obtained according to the following equation.
SUSPITV is available for standard SPI transactions, it must be set to 0 for DUAL and
QUAD mode transactions.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
SUSPITV = 0x0 … 0.5 SPICLK clock cycle.
SUSPITV = 0x1 … 1.5 SPICLK clock cycle.
……
SUSPITV = 0xE … 14.5 SPICLK clock cycle.
SUSPITV = 0xF … 15.5 SPICLK clock cycle.
Note:
For DUAL and QUAD transactions with SUSPITV must be set to 0.
[3]
CLKPOL
Clock Polarity
0 = SCLK idle low.
1 = SCLK idle high.
[2]
TXNEG
Transmit at Negative Edge
0 = The transmitted data output signal is changed at the rising edge of SCLK.
1 = The transmitted data output signal is changed at the falling edge of SCLK.
[1]
RXNEG
Receive at Negative Edge
0 = The received data input signal is latched at the rising edge of SCLK.
1 = The received data input signal is latched at the falling edge of SCLK.
[0]
SPIEN
SPI Transfer Enable
0 = Disable SPI Transfer.
1 = Enable SPI Transfer.
In Master mode, the transfer will start when there is data in the FIFO buffer after this
is set to 1. In Slave mode, the device is ready to receive data when this bit is set to
1.
Note:
All configuration should be set before writing 1 to this SPIEN bit. (e.g.: TXNEG,
RXNEG, DWIDTH, LSB, CLKP, and so on).
