ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 257 -
Revision 2.4
determined by setting of SPI1_CLKDIV, if the bit content of VARCLK is ‘1’, the output period for that bit
is determined by the SPI1_ CLKDIV.DIV1 register. The following figure shows the timing relationships
of serial clock (SCLK), to the VARCLK, the DIV0 and the DIV1 registers. A two-bit combination in the
VARCLK defines one clock cycle. The bit field VARCLK[31:30] defines the first clock cycle of SCLK.
The bit field VARCLK[29:28] defines the second clock cycle of SCLK and so on. The clock source
selections are defined in VARCLK and must be set 1 cycle before the next clock option. For example, if
there are 5 CLK1 cycle in SPICLK, the VARCLK shall set 9 ‘0’ in the MSB of VARCLK. The 10th shall
be set as ‘1’ in order to switch the next clock source is CLK2. Note that when VARCLKEN bit is set, the
setting of TXBITLEN must be programmed as 0x10 (16 bits mode only).
00000000011111111111111110000111
SPICLK
VARCLK
CLK1 (DIV)
CLK2 (DIV2)
Figure 5-62 Variable Serial Clock Frequency
5.10.5 SPI Timing Diagram
In master/slave mode, the device address/slave select (SPI_SSB) signal can be configured as active
low or active high by the SPI1_ SSCTL.SSLVL bit. In slave mode, the SPI1>- SSCTL.SSLTRIG will
determine whether the slave select signal is treated as a level triggered or edge triggered signal.
The serial clock phase and polarity is controlled by CLKP, RXNEG and TXNEG bits. The bit length of a
transfer word is configured by the TXBITLEN parameter. Whether data transmission is MSB first or LSB
first is controlled by the SPI1_CTL.LSB bit. Four examples of SPI timing diagrams for master/slave
operations and the related settings are shown as below.
SPICLK
MISO
Master Mode: CTL.SLVAE=0, CTL.LSB=0, CTL.TXNUM=0x0, CTL.TXBITLEN=0x08
MOSI
Tx0[6]
Tx0[5]
Tx0[4]
Tx0[3]
Tx0[2]
Tx0[1]
LSB
Tx0[0]
MSB
Tx0[7]
Rx0[6]
Rx0[5]
Rx0[4]
Rx0[3]
Rx0[2]
Rx0[1]
LSB
Rx0[0]
MSB
Rx0[7]
CLKP=0
CLKP=1
SPI->SS
SS.LVL=1
SS.LVL=0
1. CTL.CLKP=0, CTL.TXNEG=1, CTL.RXNEG=0 or
2. CTL.CLKP=1, CTL.TXNEG=0, CTL.RXNEG=1
Figure 5-63 SPI Timing in Master Mode
