ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.6.4
I2C Protocol Registers
The CPU interfaces to the SIO port through the following thirteen special function registers: I2C_CTL
(control register), I2C_STATUS (status register), I2C_DAT (data register), I2C_ADDRn (address
registers, n=0~3), I2C_ADDRMSKn (address mask registers, n=0~3), I2C_CLKDIV (clock rate register)
and I2C_TOCTL (Time-out counter register). Bits 31~ bit 8 of these I2C special function registers are
reserved. These bits do not have any functions and are all zero if read back.
When I2C port is enabled by setting I2CEN (I2C_CTL[6]) to high, the internal states will be controlled by
I2C_CTL and I2C logic hardware. Once a new status code is generated and stored in I2C_STATUS,
the I2C Interrupt Flag bit SI (I2C_CTL[3]) will be set automatically. If the Enable Interrupt bit INTEN
(I2C_CTL[7]) is set high at this time, the I2C interrupt will be generated. The bit field I2C_STATUS[7:3]
stores the internal state code, the lowest 3 bits of I2C_STATUS are always zero and the contents are
stable until SI is cleared by software. The base address of the I2C peripheral on theI91200 is
0x4002_0000.
5.6.4.1
Address Registers (I2C_ADDR)
I2C port is equipped with four slave address registers I2C_ADDRn (n=0~3). The contents of the register
are irrelevant when I2C is in master mode. In the slave mode, the bit field I2C_ADDRn[7:1] must be
loaded with the MCU’s own slave address. The I2C hardware will react if the contents of I2C_ADDR are
matched with the received slave address.
The I2C ports support the “General Call” function. If the GC bit (I2C_ADDRn[0]) is set the I2C port
hardware will respond to General Call address (00H). Clear GC bit to disable general call function.
When GC bit is set, the I2C is in Slave mode, it can be received the general call address by 00H after
Master send general call address to I2C bus, then it will follow status of GC mode. If it is in master
mode, the AA bit (I2C_CTL[2], Assert Acknowledge control bit) must be cleared when it will send
general call address of 00H to I2C bus.
I2C-bus controllers support multiple address recognition with four address mask registers I2ADRMn
(n=0~3). When the bit in the address mask register is set to one, it means the received corresponding
address bit is don’t-care. If the bit is set to zero, that means the received corresponding register bit
should be exact the same as address register.
5.6.4.2
Data Register (I2C_DAT)
This register contains a byte of serial data to be transmitted or a byte which has just been received. The
CPU can read from or write to this 8-bit (I2C_DAT[7:0]) directly addressable SFR while it is not in the
process of shifting a byte. This occurs when SIO is in a defined state and the serial interrupt flag (SI) is
set. Data in I2C_DAT[7:0] remains stable as long as SI bit is set. While data is being shifted out, data
on the bus is simultaneously being shifted in; I2C_DAT[7:0] always contains the last data byte present
on the bus. Thus, in the event of arbitration lost, the transition from master transmitter to slave receiver
is made with the correct data in I2C_DAT[7:0].
I2C_DAT[7:0] and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by
the SIO hardware and cannot be accessed by the CPU. Serial data is shifted through the acknowledge
bit into I2C_DAT[7:0] on the rising edges of serial clock pulses on the SCL line. When a byte has been
shifted into I2C_DAT[7:0], the serial data is available in I2C_DAT[7:0], and the acknowledge bit (ACK or
NACK) is returned by the control logic during the ninth clock pulse. Serial data is shifted out from
I2C_DAT[7:0] on the falling edges of SCL clock pulses, and is shifted into I2C_DAT[7:0] on the rising
edges of SCL clock pulses.
