ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
7.8.3.1
SARADC Clock Generator
The SARADC engine has four clock sources selected by 2 bits SARADCSEL, the SARADC clock divided by 8 bits
prescaler with the formula.
The SARADC clock frequency = (SARADC clock source frequency)/(SA1).
Where the 8 bits SARADCDIV is located in register CLKDIV0[31:24].
11
10
01
00
CLK_10K
HCLK
CLK_32K
SARADCCKSEL(CLK_CLKSEL1[25:24])
SARADCEN(CLK_APBCLK0[17])
SARADC_CLK
1/(SAR 1)
SARADCDIV(CLK_CLKDIV0[31:24])
CLK_49M
Note: Before clock switching, both the pre-selected and newly
selected clock sources must be turned on and stable.
Figure 7-21 SARADC Clock Generator
7.8.3.2
Single Mode
I
n single mode, A/D conversion is performed only once on the specified single channel. The operations are as follows:
1. A/D conversion will be started when the SWTRG bit of CTL is set to 1 by software.
2. When A/D conversion is finished, the result is stored in the A/D data register corresponding to the channel.
3. The ADEF bit of STATUS register will be set to 1. If the ADCIE bit of CTL register is set to 1, the SARADC
interrupt will be asserted.
4. The SWTRG bit remains 1 during A/D conversion. When A/D conversion ends, the SWTRG bit is
automatically cleared to 0 and the A/D converter enters idle state.
Note: If software enables more than one channel in single mode, the channel with the smallest number will be
selected and the other enabled channels will be ignored.
