ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 334 -
Revision 2.4
[15:12]
WAINTSEL
Wrap Interrupt Select
x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be
generated when half each PDMA transfer is complete. For example if
PDMA_TXCNTn = 32 then an interrupt could be generated when 16 bytes were
sent.
xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be
generated when each PDMA transfer is wrapped. For example if PDMA_TXCNTn =
32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps
around.
x1x1: Both half and w interrupts generated.
[11:8]
Reserved
[7:6]
DASEL
Destination Address Select
This parameter determines the behavior of the current destination address register
with each PDMA transfer. It can either be fixed, incremented or wrapped.
00 = Transfer Destination Address is incremented.
01 = Reserved.
10 = Transfer Destination Address is fixed (Used when data transferred from multiple
addresses to a single destination such as peripheral FIFO input).
11 = Transfer Destination Address is wrapped.
When PDMA_CURTXCNTn (Current Byte Count) equals zero, the
PDMA_CURDADDR (Current Destination Address) and PDMA_CURTXCNTn
registers will be reloaded from the PDMA_DADDRn (Destination Address) and
PDMA_TXCNTn (Byte Count) registers automatically and PDMA will start another
transfer.
Cycle continues until software sets PDMA_CTLn.CHEN =0.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer
but the remaining data in the SBUF will not be transferred to the destination address.
[5:4]
SASEL
Source Address Select
This parameter determines the behavior of the current source address register with
each PDMA transfer. It can either be fixed, incremented or wrapped.
00 = Transfer Source address is incremented.
01 = Reserved.
10 = Transfer Source address is fixed.
11 = Transfer Source address is wrapped.
When PDMA_CURTXCNTn (Current Byte Count) equals zero, the
PDMA_CURSADDRn (Current Source Address) and PDMA_CURTXCNTn registers
will be reloaded from the PDMA_SADDRn (Source Address) and PDMA_TXCNT
(Byte Count) registers automatically and PDMA will start another transfer.
Cycle continues until software sets PDMA_CTLn.CHEN = 0.
When PDMA_CTLn.CHEN is disabled, the PDMA will complete the active transfer
but the remaining data in the SBUF will not be transferred to the destination address.
[3:2]
MODESEL
PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values
are:
00 = Memory to Memory mode (SRAM-to-SRAM).
01 = IP to Memory mode (APB-to-SRAM).
10 = Memory to IP mode (SRAM-to-APB).
[1]
SWRST
Software Engine Reset
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit will reset the internal state machine and pointers. The
contents of the control register will not be cleared. This bit will auto clear after a few
clock cycles.
