ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 388 -
Revision 2.4
SD Analog Block Control Register(SDADC_SDCHOP)
Register
Offset
R/W
Description
Reset Value
SDADC_SDCHOP S0x20 R/W
Sigma Delta Analog Block Control Register
0x001c_1021
31
30
29
28
27
26
25
24
AUDIOPATHSEL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
23
22
21
20
19
18
17
16
Reserved
PGAADCDC
PGAADCUP
PGABYPS
PGACLASSA
PGACMLCKADJ
15
14
13
12
11
10
9
8
PGACMLCK
PGADISCH
PGAGAIN
PGAIBLOOP
PGAIBCTR
PGAMODE
7
6
5
4
3
2
1
0
PGAMODE
PGAMUTE
PGAPU
Reserved
BIAS
PD
Bits
Description
[31:30]
AUDIOPATHSEL
Audio Path Selection, Connect SDADC input to
00 = PGA (default)
01 = MICN and MICP pins (bypass PGA)
10 = Reserved
11 = Reserved
[29:23]
Reserved
Reserved
[22:21]
PGA_ADCDC
Action takes effect when PGA_DISCH=1
Bit[21]: ACDC_CTRL[0] charges INP to VREF
Bit[22]: ACDC_CTRL[1] charges INN to VREF
00=Default
[20]
PGA_HZMODE
Select input impedance
0 = 12k Ohm input impedance
1 = 500k Ohm input impedance (default)
[19]
PGA_TRIMOBC
Trim current in output driver
0=disable
1=enable (default)
[18]
PGA_CLASSA
Enable Class A mode of operation
0 = Class AB
1 = Class A (default)