Nuvoton ISD91200 Series, Technical Reference Manual

Page: 319 / 473

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 319 - Revision 2.4
5.14.7 Register Description
I2S Control Register (I2S_CTL)
Register Offset R/W Description Reset Value
I2S_CTL 0x00 R/W I2S Control Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved Reserved RXPDMAEN TXPDMAEN RXCLR TXCLR LZCEN RZCEN
15 14 13 12 11 10 9 8
MCLKEN RXTH TXTH SLAVE
7 6 5 4 3 2 1 0
FORMAT MONO WDWIDTH MUTE RXEN TXEN I2SEN
Table 5-132 I2S Control Register (I2S_CTL, address 0x400A_0000)
Bits Description
[31:22] Reserved Reserved.
[21] RXPDMAEN
Enable Receive DMA
When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to
SRAM if FIFO is not empty.
0 = Disable RX DMA.
1 = Enable RX DMA.
[20] TXPDMAEN
Enable Transmit DMA
When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit
FIFO if FIFO is not full.
0 = Disable TX DMA.
1 = Enable TX DMA.
[19] RXCLR
Clear Receive FIFO
Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and
I2S_STATUS.RXCNT[3:0] returns to zero and receive FIFO becomes empty.
This bit is cleared by hardware automatically when clear operation complete.
[18] TXCLR
Clear Transmit FIFO
Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and
I2S_STATUS.TXCNT[3:0] returns to zero and transmit FIFO becomes empty. Data
in transmit FIFO is not changed.
This bit is cleared by hardware automatically when clear operation complete.
[17] LZCEN
Left Channel Zero Cross Detect Enable
If this bit is set to 1, when left channel data sign bit changes, or data bits are all zero,
the LZCIF flag in I2S_STATUS register will be set to 1.
0 = Disable left channel zero cross detect.
1 = Enable left channel zero cross detect.