Nuvoton ISD91200 Series, Technical Reference Manual

Page: 332 / 473

ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 332 - Revision 2.4
5.15.5 Register Map
R : read only, W : write only, R/W : both read and write, C : Only value 0 can be written
Register Offset R/W Description Reset Value
PDMA Base Address:
PDMAn_BA = 0x500(n*0x100)
n=0,1,2,3
PDMA Global Control Base Address:
PDMA_GCR_BA = 0x5000_8F00
PDMA_CTLn P0x00 R/W PDMA Control Register of Channel n 0x0000_0000
PDMA_SADDRn P0x04 R/W
PDMA Transfer Source Address Register of
Channel n
0x4000_0000
PDMA_DADDRn P0x08 R/W
PDMA Transfer Destination Address Register of
Channel n
0x4000_0000
PDMA_TXCNTn P0x0C R/W PDMA Transfer Byte Count Register of Channel n 0x0000_0000
PDMA_INTPNTn P0x10 R
PDMA Internal Buffer Pointer Register of Channel
n
0xXXXX_XX00
PDMA_CURSADDRn P0x14 R
PDMA Current Source Address Register of
Channel n
0xFFFF_FFFF
PDMA_CURDADDRn P0x18 R
PDMA Current Destination Address Register of
Channel n
0xFFFF_FFFF
PDMA_CURTXCNTn P0x1C R
PDMA Current Transfer Byte Count Register of
Channel n
0x0000_0000
PDMA_INTENn P0x20 R/W
PDMA Interrupt Enable Control Register of
Channel n
0x0000_0001
PDMA_INTSTSn P0x24 R/W PDMA Interrupt Status Register of Channel n 0x0000_0000
PDMA_SPANn P0x34 R PDMA Span Increment Register of Channel n 0x0000_0000
PDMA_CURSPANn P0x38 R/W
PDMA Current Span Increment Register of
Channel n
0x0000_0000
PDMA_GCTL
PDMA0x
00
R/W PDMA Global Control Register 0x0000_0000
PDMA_SVCSEL0
PDMA0x
04
R/W PDMA Service Selection Control Register 0 0xFFFF_FFFF
PDMA_SVCSEL1
PDMA0x
08
R/W PDMA Service Selection Control Register 1 0xFFFF_FFFF
PDMA_GINTSTS
PDMA0x
0C
R PDMA Global Interrupt Status Register 0x0000_0000