ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
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Revision 2.4
5.15 PDMA Controller
5.15.1 Overview
The I91200 incorporates a Peripheral Direct Memory Access (PDMA) controller that transfers data
between SRAM and APB devices. The PDMA has four channels of DMA PDMA CH0~CH3). PDMA
transfers are unidirectional and can be Peripheral-to-SRAM,SRAM-to-Peripheral or SRAM-to-SRAM.
The peripherals available for PDMA transfer are SPI, UART, I2S, SDADC, SARADC and DPWM.
PDMA operation is controlled for each channel by configuring a source and destination address and
specifying a number of bytes to transfer. Source and destination addresses can be fixed, automatically
increment by the transfer size, update by an arbitrary value (span mode) or wrap around a circular
buffer. When PDMA operation is complete, controller can be configured to provide CPU with an
interrupt.
5.15.2 Features
Provides access to SPI, UART, I2S, SDADC and DPWM peripherals.
AMBA AHB master/slave interface, transfers can occur concurrently with CPU access to flash
memory.
PDMA source and destination addressing modes allow fixed, incrementing, wrap-around and
spanned addressing.
5.15.3 Block Diagram
SRAM
AHB ARB
CortexM0
APB Bridge
AHB ARB
PDMA
Controller
AHB BUS2
AHB BUS1
APB Bus
To
Peripherals
PDMA
Control
Registers
PDMA
Service
Request
Signals
from
Peripherals
Figure 5-82 PDMA Controller Block Diagram
