ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 123 -
Revision 2.4
Clock Source Select Control Register 1
（
CLK_CLKSEL1
）
Clock multiplexors are a glitch free design to ensure smooth transitions between asynchronous clock
sources. As such, both the current clock source and the target clock source must be enabled for
switching to occur. Beware when switching from a low speed clock to a high speed clock that low
speed clock remains on for at least one period before disabling.
Register
Offset
R/W
Description
Reset Value
CLK_CLKSEL1
0x14 R/W
Clock Source Select Control Register 1
0xF000_7703
31
30
29
28
27
26
25
24
PWM0CH23SEL
PWM0CH01SEL
Reserved
SARADCSEL
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
TMR1SEL
Reserved
TMR0SEL
7
6
5
4
3
2
1
0
Reserved
DPWMSEL
ADCSEL
WDTSEL
Table 5-42 Clock Source Select Register 1 (CLK_CLKSEL1, address 0x5000_0214)
Bits
Description
[31:30]
PWM0CH23SEL
PWM0CH23 Clock Source Select
PWM0 CH2 and CH3 uses the same clock source, and pre-scaler
00 = clock source from LIRC.
01 = clock source from LXT.
10 = clock source from HCLK.
11 = clock source from HIRC.(default)
[29:28]
PWM0CH01SEL
PWM0CH01 Clock Source Select
PWM0 CH0 and CH1 uses the same clock source, and pre-scaler
00 = clock source from LIRC.
01 = clock source from LXT.
10 = clock source from HCLK.
11 = clock source from HIRC.(default)
[27:26]
Reserved
[25:24]
SARADCSEL
SAR ADC Clock Source Select
00 = clock source from HCLK (default)
01 = clock source from LIRC.
10 = clock source from HIRC.
11 = clock source from LXT.
[23:15]
Reserved
