ISD91200 Series Technical Reference Manual
Release Date: Sep 16, 2019
- 418 -
Revision 2.4
Frequency Measurement Cycle (ANA_FQMMCYC)
Register
Offset
R/W
Description
Reset Value
ANA_FQMMCYC
0x9C
R/W
Frequency Measurement Cycle Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
FQMMCYC
15
14
13
12
11
10
9
8
FQMMCYC
7
6
5
4
3
2
1
0
FQMMCYC
Table 7-14 Frequency Measurement Cycle Register (ANA_FQMMCYC, address 0x4008_009C).
Bits
Description
[31:24]
Reserved
Reserved.
[23:0]
FQMMCYC
Frequency Measurement Cycles
Number of reference clock periods plus one to measure target clock (PCLK). For example if
reference clock is OSC32K (T = 30.5175µs), FQMMCYC = 7, then measurement period would be
30.5175*(7+1) = 244.1µs. This address access same register as ANA_FQMMCTL but allows
access to more bits of register.